src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "main/macros.h"
  33 #include "main/enums.h"
  34 #include "shader/prog_parameter.h"
  35 #include "shader/prog_statevars.h"
  36 #include "intel_batchbuffer.h"
  37
  38 static void
  39 upload_wm_state(struct brw_context *brw)
  40 {
  41    struct intel_context *intel = &brw->intel;
  42    GLcontext *ctx = &intel->ctx;
  43    const struct brw_fragment_program *fp =
  44       brw_fragment_program_const(brw->fragment_program);
  45    unsigned int nr_params = fp->program.Base.Parameters->NumParameters;
  46    drm_intel_bo *constant_bo;
  47    int i;
  48    uint32_t dw2, dw4, dw5, dw6;
  49
  50    dw2 = dw4 = dw5 = dw6 = 0;
  51    dw4 |= GEN6_WM_STATISTICS_ENABLE;
  52    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
  53    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
  54
  55    /* BRW_NEW_NR_SURFACES */
  56    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
  57
  58    /* CACHE_NEW_SAMPLER */
  59    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
  60    dw4 |= (1 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
  61
  62    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
  63    dw5 |= GEN6_WM_DISPATCH_ENABLE;
  64
  65    /* BRW_NEW_FRAGMENT_PROGRAM */
  66    if (fp->isGLSL)
  67       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
  68    else
  69       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
  70
  71    /* _NEW_LINE */
  72    if (ctx->Line.StippleFlag)
  73       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
  74
  75    /* _NEW_POLYGONSTIPPLE */
  76    if (ctx->Polygon.StippleFlag)
  77       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
  78
  79    /* BRW_NEW_FRAGMENT_PROGRAM */
  80    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
  81       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
  82    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
  83       dw5 |= GEN6_WM_COMPUTED_DEPTH;
  84
  85    /* _NEW_COLOR */
  86    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
  87       dw5 |= GEN6_WM_KILL_ENABLE;
  88
  89    /* This should probably be FS inputs read */
  90    dw6 |= brw_count_bits(brw->vs.prog_data->outputs_written) <<
  91       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
  92
  93    BEGIN_BATCH(9);
  94    OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
  95    OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  96    OUT_BATCH(dw2);
  97    OUT_BATCH(0); /* scratch space base offset */
  98    OUT_BATCH(dw4);
  99    OUT_BATCH(dw5);
 100    OUT_BATCH(dw6);
 101    OUT_BATCH(0); /* kernel 1 pointer */
 102    OUT_BATCH(0); /* kernel 2 pointer */
 103    ADVANCE_BATCH();
 104
 105    intel_batchbuffer_emit_mi_flush(intel->batch);
 106
 107    if (fp->use_const_buffer || nr_params == 0) {
 108       /* Disable the push constant buffers. */
 109       BEGIN_BATCH(5);
 110       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
 111       OUT_BATCH(0);
 112       OUT_BATCH(0);
 113       OUT_BATCH(0);
 114       OUT_BATCH(0);
 115       ADVANCE_BATCH();
 116    } else {
 117       /* Updates the ParamaterValues[i] pointers for all parameters of the
 118        * basic type of PROGRAM_STATE_VAR.
 119        */
 120       _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 121
 122       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
 123                                        nr_params * 4 * sizeof(float),
 124                                        4096);
 125       intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
 126       for (i = 0; i < nr_params; i++) {
 127          memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
 128                 fp->program.Base.Parameters->ParameterValues[i],
 129                 4 * sizeof(float));
 130       }
 131       intel_bo_unmap_gtt_preferred(intel, constant_bo);
 132
 133       BEGIN_BATCH(5);
 134       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
 135                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 136                 (5 - 2));
 137       OUT_RELOC(constant_bo,
 138                 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
 139                 ALIGN(nr_params, 2) / 2 - 1);
 140       OUT_BATCH(0);
 141       OUT_BATCH(0);
 142       OUT_BATCH(0);
 143       ADVANCE_BATCH();
 144
 145       drm_intel_bo_unreference(constant_bo);
 146    }
 147
 148    intel_batchbuffer_emit_mi_flush(intel->batch);
 149 }
 150
 151 const struct brw_tracked_state gen6_wm_state = {
 152    .dirty = {
 153       .mesa  = _NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR,
 154       .brw   = (BRW_NEW_CURBE_OFFSETS |
 155                 BRW_NEW_FRAGMENT_PROGRAM |
 156                 BRW_NEW_NR_WM_SURFACES |
 157                 BRW_NEW_URB_FENCE |
 158                 BRW_NEW_BATCH),
 159       .cache = CACHE_NEW_SAMPLER
 160    },
 161    .emit = upload_wm_state,
 162 };