2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "main/macros.h"
33 #include "main/enums.h"
34 #include "shader/prog_parameter.h"
35 #include "shader/prog_statevars.h"
36 #include "intel_batchbuffer.h"
39 upload_wm_state(struct brw_context
*brw
)
41 struct intel_context
*intel
= &brw
->intel
;
42 GLcontext
*ctx
= &intel
->ctx
;
43 const struct brw_fragment_program
*fp
=
44 brw_fragment_program_const(brw
->fragment_program
);
45 unsigned int nr_params
= fp
->program
.Base
.Parameters
->NumParameters
;
46 drm_intel_bo
*constant_bo
;
48 uint32_t dw2
, dw4
, dw5
, dw6
;
50 if (fp
->use_const_buffer
|| nr_params
== 0) {
51 /* Disable the push constant buffers. */
53 OUT_BATCH(CMD_3D_CONSTANT_PS_STATE
<< 16 | (5 - 2));
60 /* Updates the ParamaterValues[i] pointers for all parameters of the
61 * basic type of PROGRAM_STATE_VAR.
63 _mesa_load_state_parameters(ctx
, fp
->program
.Base
.Parameters
);
65 constant_bo
= drm_intel_bo_alloc(intel
->bufmgr
, "WM constant_bo",
66 nr_params
* 4 * sizeof(float),
68 intel_bo_map_gtt_preferred(intel
, constant_bo
, GL_TRUE
);
69 for (i
= 0; i
< nr_params
; i
++) {
70 memcpy((char *)constant_bo
->virtual + i
* 4 * sizeof(float),
71 fp
->program
.Base
.Parameters
->ParameterValues
[i
],
74 intel_bo_unmap_gtt_preferred(intel
, constant_bo
);
77 OUT_BATCH(CMD_3D_CONSTANT_PS_STATE
<< 16 |
78 GEN6_CONSTANT_BUFFER_0_ENABLE
|
80 OUT_RELOC(constant_bo
,
81 I915_GEM_DOMAIN_RENDER
, 0, /* XXX: bad domain */
82 ALIGN(nr_params
, 2) / 2 - 1);
88 drm_intel_bo_unreference(constant_bo
);
91 intel_batchbuffer_emit_mi_flush(intel
->batch
);
93 dw2
= dw4
= dw5
= dw6
= 0;
94 dw4
|= GEN6_WM_STATISTICS_ENABLE
;
95 dw5
|= GEN6_WM_LINE_AA_WIDTH_1_0
;
96 dw5
|= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5
;
98 /* BRW_NEW_NR_SURFACES */
99 dw2
|= brw
->wm
.nr_surfaces
<< GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT
;
101 /* CACHE_NEW_SAMPLER */
102 dw2
|= (ALIGN(brw
->wm
.sampler_count
, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT
;
103 dw4
|= (1 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0
);
105 dw5
|= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT
;
106 dw5
|= GEN6_WM_DISPATCH_ENABLE
;
108 /* BRW_NEW_FRAGMENT_PROGRAM */
110 dw5
|= GEN6_WM_8_DISPATCH_ENABLE
;
112 dw5
|= GEN6_WM_16_DISPATCH_ENABLE
;
115 if (ctx
->Line
.StippleFlag
)
116 dw5
|= GEN6_WM_LINE_STIPPLE_ENABLE
;
118 /* _NEW_POLYGONSTIPPLE */
119 if (ctx
->Polygon
.StippleFlag
)
120 dw5
|= GEN6_WM_POLYGON_STIPPLE_ENABLE
;
122 /* BRW_NEW_FRAGMENT_PROGRAM */
123 if (fp
->program
.Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
))
124 dw5
|= GEN6_WM_USES_SOURCE_DEPTH
| GEN6_WM_USES_SOURCE_W
;
125 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
126 dw5
|= GEN6_WM_COMPUTED_DEPTH
;
129 if (fp
->program
.UsesKill
|| ctx
->Color
.AlphaEnabled
)
130 dw5
|= GEN6_WM_KILL_ENABLE
;
132 /* This should probably be FS inputs read */
133 dw6
|= brw_count_bits(brw
->vs
.prog_data
->outputs_written
) <<
134 GEN6_WM_NUM_SF_OUTPUTS_SHIFT
;
137 OUT_BATCH(CMD_3D_WM_STATE
<< 16 | (9 - 2));
138 OUT_RELOC(brw
->wm
.prog_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
140 OUT_BATCH(0); /* scratch space base offset */
144 OUT_BATCH(0); /* kernel 1 pointer */
145 OUT_BATCH(0); /* kernel 2 pointer */
148 intel_batchbuffer_emit_mi_flush(intel
->batch
);
151 const struct brw_tracked_state gen6_wm_state
= {
153 .mesa
= _NEW_LINE
| _NEW_POLYGONSTIPPLE
| _NEW_COLOR
,
154 .brw
= (BRW_NEW_CURBE_OFFSETS
|
155 BRW_NEW_FRAGMENT_PROGRAM
|
156 BRW_NEW_NR_WM_SURFACES
|
159 .cache
= CACHE_NEW_SAMPLER
161 .emit
= upload_wm_state
,