src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/program.h"
  34 #include "program/prog_parameter.h"
  35 #include "program/prog_statevars.h"
  36 #include "intel_batchbuffer.h"
  37
  38 static void
  39 gen6_upload_wm_push_constants(struct brw_context *brw)
  40 {
  41    struct gl_context *ctx = &brw->ctx;
  42    /* BRW_NEW_FRAGMENT_PROGRAM */
  43    const struct brw_fragment_program *fp =
  44       brw_fragment_program_const(brw->fragment_program);
  45    /* CACHE_NEW_WM_PROG */
  46    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  47
  48    /* Updates the ParameterValues[i] pointers for all parameters of the
  49     * basic type of PROGRAM_STATE_VAR.
  50     */
  51    /* XXX: Should this happen somewhere before to get our state flag set? */
  52    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  53
  54    if (prog_data->base.nr_params == 0) {
  55       brw->wm.base.push_const_size = 0;
  56    } else {
  57       float *constants;
  58       unsigned int i;
  59
  60       constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
  61                                   prog_data->base.nr_params * sizeof(float),
  62                                   32, &brw->wm.base.push_const_offset);
  63
  64       for (i = 0; i < prog_data->base.nr_params; i++) {
  65          constants[i] = *prog_data->base.param[i];
  66       }
  67
  68       if (0) {
  69          fprintf(stderr, "WM constants:\n");
  70          for (i = 0; i < prog_data->base.nr_params; i++) {
  71             if ((i & 7) == 0)
  72                fprintf(stderr, "g%d: ", prog_data->first_curbe_grf + i / 8);
  73             fprintf(stderr, "%8f ", constants[i]);
  74             if ((i & 7) == 7)
  75                fprintf(stderr, "\n");
  76          }
  77          if ((i & 7) != 0)
  78             fprintf(stderr, "\n");
  79          fprintf(stderr, "\n");
  80       }
  81
  82       brw->wm.base.push_const_size = ALIGN(prog_data->base.nr_params, 8) / 8;
  83    }
  84
  85    if (brw->gen >= 7) {
  86       gen7_upload_constant_state(brw, &brw->wm.base, true,
  87                                  _3DSTATE_CONSTANT_PS);
  88    }
  89 }
  90
  91 const struct brw_tracked_state gen6_wm_push_constants = {
  92    .dirty = {
  93       .mesa  = _NEW_PROGRAM_CONSTANTS,
  94       .brw   = (BRW_NEW_BATCH |
  95                 BRW_NEW_FRAGMENT_PROGRAM |
  96                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
  97       .cache = CACHE_NEW_WM_PROG,
  98    },
  99    .emit = gen6_upload_wm_push_constants,
 100 };
 101
 102 static void
 103 upload_wm_state(struct brw_context *brw)
 104 {
 105    struct gl_context *ctx = &brw->ctx;
 106    const struct brw_fragment_program *fp =
 107       brw_fragment_program_const(brw->fragment_program);
 108    uint32_t dw2, dw4, dw5, dw6;
 109
 110    /* _NEW_BUFFERS */
 111    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
 112
 113     /* CACHE_NEW_WM_PROG */
 114    if (brw->wm.prog_data->base.nr_params == 0) {
 115       /* Disable the push constant buffers. */
 116       BEGIN_BATCH(5);
 117       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 118       OUT_BATCH(0);
 119       OUT_BATCH(0);
 120       OUT_BATCH(0);
 121       OUT_BATCH(0);
 122       ADVANCE_BATCH();
 123    } else {
 124       BEGIN_BATCH(5);
 125       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 126                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 127                 (5 - 2));
 128       /* Pointer to the WM constant buffer.  Covered by the set of
 129        * state flags from gen6_upload_wm_push_constants.
 130        */
 131       OUT_BATCH(brw->wm.base.push_const_offset +
 132                 brw->wm.base.push_const_size - 1);
 133       OUT_BATCH(0);
 134       OUT_BATCH(0);
 135       OUT_BATCH(0);
 136       ADVANCE_BATCH();
 137    }
 138
 139    dw2 = dw4 = dw5 = dw6 = 0;
 140    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 141    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 142    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 143
 144    /* Use ALT floating point mode for ARB fragment programs, because they
 145     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 146     * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
 147     * to differentiate between the GLSL and non-GLSL cases.
 148     */
 149    if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 150       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 151
 152    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
 153            GEN6_WM_SAMPLER_COUNT_SHIFT;
 154
 155    /* CACHE_NEW_WM_PROG */
 156    dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
 157            GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 158
 159    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 160
 161    /* CACHE_NEW_WM_PROG */
 162
 163    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 164     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 165     * is successfully compiled. In majority of the cases that bring us
 166     * better performance than 'SIMD8 only' dispatch.
 167     */
 168    int min_inv_per_frag =
 169       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
 170    assert(min_inv_per_frag >= 1);
 171
 172    if (brw->wm.prog_data->prog_offset_16) {
 173       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 174
 175       if (min_inv_per_frag == 1) {
 176          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 177          dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 178                  GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 179          dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 180                  GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 181       } else
 182          dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 183                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 184    }
 185    else {
 186       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 187       dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 188               GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 189    }
 190
 191    /* CACHE_NEW_WM_PROG | _NEW_COLOR */
 192    if (brw->wm.prog_data->dual_src_blend &&
 193        (ctx->Color.BlendEnabled & 1) &&
 194        ctx->Color.Blend[0]._UsesDualSrc) {
 195       dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
 196    }
 197
 198    /* _NEW_LINE */
 199    if (ctx->Line.StippleFlag)
 200       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 201
 202    /* _NEW_POLYGON */
 203    if (ctx->Polygon.StippleFlag)
 204       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 205
 206    /* BRW_NEW_FRAGMENT_PROGRAM */
 207    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
 208       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 209    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 210       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 211    /* CACHE_NEW_WM_PROG */
 212    dw6 |= brw->wm.prog_data->barycentric_interp_modes <<
 213       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 214
 215    /* _NEW_COLOR, _NEW_MULTISAMPLE */
 216    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
 217        ctx->Multisample.SampleAlphaToCoverage ||
 218        brw->wm.prog_data->uses_omask)
 219       dw5 |= GEN6_WM_KILL_ENABLE;
 220
 221    /* _NEW_BUFFERS | _NEW_COLOR */
 222    if (brw_color_buffer_write_enabled(brw) ||
 223        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 224       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 225    }
 226
 227    /* From the SNB PRM, volume 2 part 1, page 278:
 228     * "This bit is inserted in the PS payload header and made available to
 229     * the DataPort (either via the message header or via header bypass) to
 230     * indicate that oMask data (one or two phases) is included in Render
 231     * Target Write messages. If present, the oMask data is used to mask off
 232     * samples."
 233     */
 234     if(brw->wm.prog_data->uses_omask)
 235       dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
 236
 237    /* CACHE_NEW_WM_PROG */
 238    dw6 |= brw->wm.prog_data->num_varying_inputs <<
 239       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 240    if (multisampled_fbo) {
 241       /* _NEW_MULTISAMPLE */
 242       if (ctx->Multisample.Enabled)
 243          dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 244       else
 245          dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 246
 247       if (min_inv_per_frag > 1)
 248          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 249       else {
 250          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 251
 252          /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping
 253           * (Dispatch Size) Control"), p.334:
 254           *
 255           *     Note: in the table below, the Valid column indicates which
 256           *     products that combination is supported on. Combinations of
 257           *     dispatch enables not listed in the table are not available on
 258           *     any product.
 259           *
 260           *     A: Valid on all products
 261           *
 262           *     B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 263           *     computed depth.
 264           *
 265           *     D: Valid on all products, except when in non-1x PERSAMPLE mode
 266           *     (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x
 267           *     PERPIXEL mode with pixel shader computed depth.
 268           *
 269           *     E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 270           *     computed depth.
 271           *
 272           *     F: Valid on all products, except not valid on [DevSNB] if 4x
 273           *     PERPIXEL mode with pixel shader computed depth.
 274           *
 275           * In the table that follows, the only entry with "A" in the Valid
 276           * column is the entry where only 8 pixel dispatch is enabled.
 277           * Therefore, when we are in PERPIXEL mode with pixel shader computed
 278           * depth, we need to disable SIMD16 dispatch.
 279           */
 280          if (dw5 & GEN6_WM_COMPUTED_DEPTH)
 281             dw5 &= ~GEN6_WM_16_DISPATCH_ENABLE;
 282       }
 283    } else {
 284       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 285       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 286    }
 287
 288    /* From the SNB PRM, volume 2 part 1, page 281:
 289     * "If the PS kernel does not need the Position XY Offsets
 290     * to compute a Position XY value, then this field should be
 291     * programmed to POSOFFSET_NONE."
 292     *
 293     * "SW Recommendation: If the PS kernel needs the Position Offsets
 294     * to compute a Position XY value, this field should match Position
 295     * ZW Interpolation Mode to ensure a consistent position.xyzw
 296     * computation."
 297     * We only require XY sample offsets. So, this recommendation doesn't
 298     * look useful at the moment. We might need this in future.
 299     */
 300    if (brw->wm.prog_data->uses_pos_offset)
 301       dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
 302    else
 303       dw6 |= GEN6_WM_POSOFFSET_NONE;
 304
 305    BEGIN_BATCH(9);
 306    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 307    if (brw->wm.prog_data->prog_offset_16 && min_inv_per_frag > 1)
 308       OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 309    else
 310       OUT_BATCH(brw->wm.base.prog_offset);
 311    OUT_BATCH(dw2);
 312    if (brw->wm.prog_data->total_scratch) {
 313       OUT_RELOC(brw->wm.base.scratch_bo,
 314                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 315                 ffs(brw->wm.prog_data->total_scratch) - 11);
 316    } else {
 317       OUT_BATCH(0);
 318    }
 319    OUT_BATCH(dw4);
 320    OUT_BATCH(dw5);
 321    OUT_BATCH(dw6);
 322    OUT_BATCH(0); /* kernel 1 pointer */
 323    /* kernel 2 pointer */
 324    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 325    ADVANCE_BATCH();
 326 }
 327
 328 const struct brw_tracked_state gen6_wm_state = {
 329    .dirty = {
 330       .mesa  = (_NEW_LINE |
 331                 _NEW_COLOR |
 332                 _NEW_BUFFERS |
 333                 _NEW_PROGRAM_CONSTANTS |
 334                 _NEW_POLYGON |
 335                 _NEW_MULTISAMPLE),
 336       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 337                 BRW_NEW_BATCH |
 338                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 339       .cache = (CACHE_NEW_WM_PROG)
 340    },
 341    .emit = upload_wm_state,
 342 };