src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/prog_parameter.h"
  34 #include "program/prog_statevars.h"
  35 #include "intel_batchbuffer.h"
  36
  37 static void
  38 prepare_wm_constants(struct brw_context *brw)
  39 {
  40    struct intel_context *intel = &brw->intel;
  41    struct gl_context *ctx = &intel->ctx;
  42    const struct brw_fragment_program *fp =
  43       brw_fragment_program_const(brw->fragment_program);
  44
  45    drm_intel_bo_unreference(brw->wm.push_const_bo);
  46    brw->wm.push_const_bo = NULL;
  47
  48    /* Updates the ParamaterValues[i] pointers for all parameters of the
  49     * basic type of PROGRAM_STATE_VAR.
  50     */
  51    /* XXX: Should this happen somewhere before to get our state flag set? */
  52    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  53
  54    if (brw->wm.prog_data->nr_params != 0) {
  55       float *constants;
  56       unsigned int i;
  57
  58       brw->wm.push_const_bo = drm_intel_bo_alloc(intel->bufmgr,
  59                                                  "WM constant_bo",
  60                                                  brw->wm.prog_data->nr_params *
  61                                                  sizeof(float),
  62                                                  4096);
  63       drm_intel_gem_bo_map_gtt(brw->wm.push_const_bo);
  64       constants = brw->wm.push_const_bo->virtual;
  65       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  66          constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
  67                                       *brw->wm.prog_data->param[i]);
  68       }
  69       drm_intel_gem_bo_unmap_gtt(brw->wm.push_const_bo);
  70    }
  71 }
  72
  73 const struct brw_tracked_state gen6_wm_constants = {
  74    .dirty = {
  75       .mesa  = _NEW_PROGRAM_CONSTANTS,
  76       .brw   = BRW_NEW_FRAGMENT_PROGRAM,
  77       .cache = 0,
  78    },
  79    .prepare = prepare_wm_constants,
  80 };
  81
  82 static void
  83 upload_wm_state(struct brw_context *brw)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86    struct gl_context *ctx = &intel->ctx;
  87    const struct brw_fragment_program *fp =
  88       brw_fragment_program_const(brw->fragment_program);
  89    uint32_t dw2, dw4, dw5, dw6;
  90
  91    /* CACHE_NEW_WM_PROG */
  92    if (brw->wm.prog_data->nr_params == 0) {
  93       /* Disable the push constant buffers. */
  94       BEGIN_BATCH(5);
  95       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
  96       OUT_BATCH(0);
  97       OUT_BATCH(0);
  98       OUT_BATCH(0);
  99       OUT_BATCH(0);
 100       ADVANCE_BATCH();
 101    } else {
 102       BEGIN_BATCH(5);
 103       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
 104                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 105                 (5 - 2));
 106       OUT_RELOC(brw->wm.push_const_bo,
 107                 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
 108                 ALIGN(brw->wm.prog_data->nr_params,
 109                       brw->wm.prog_data->dispatch_width) / 8 - 1);
 110       OUT_BATCH(0);
 111       OUT_BATCH(0);
 112       OUT_BATCH(0);
 113       ADVANCE_BATCH();
 114    }
 115
 116    dw2 = dw4 = dw5 = dw6 = 0;
 117    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 118    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 119    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 120
 121    /* BRW_NEW_NR_WM_SURFACES */
 122    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 123
 124    /* CACHE_NEW_SAMPLER */
 125    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
 126    dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 127            GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 128
 129    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 130
 131    /* CACHE_NEW_WM_PROG */
 132    if (brw->wm.prog_data->dispatch_width == 8)
 133       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 134    else
 135       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 136
 137    /* _NEW_LINE */
 138    if (ctx->Line.StippleFlag)
 139       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 140
 141    /* _NEW_POLYGONSTIPPLE */
 142    if (ctx->Polygon.StippleFlag)
 143       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 144
 145    /* BRW_NEW_FRAGMENT_PROGRAM */
 146    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 147       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 148    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 149       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 150
 151    /* _NEW_COLOR */
 152    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
 153       dw5 |= GEN6_WM_KILL_ENABLE;
 154
 155    if (brw_color_buffer_write_enabled(brw) ||
 156        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 157       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 158    }
 159
 160    dw6 |= GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 161
 162    dw6 |= brw_count_bits(brw->fragment_program->Base.InputsRead) <<
 163       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 164
 165    BEGIN_BATCH(9);
 166    OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
 167    OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 168    OUT_BATCH(dw2);
 169    OUT_BATCH(0); /* scratch space base offset */
 170    OUT_BATCH(dw4);
 171    OUT_BATCH(dw5);
 172    OUT_BATCH(dw6);
 173    OUT_BATCH(0); /* kernel 1 pointer */
 174    OUT_BATCH(0); /* kernel 2 pointer */
 175    ADVANCE_BATCH();
 176 }
 177
 178 const struct brw_tracked_state gen6_wm_state = {
 179    .dirty = {
 180       .mesa  = (_NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR | _NEW_BUFFERS |
 181                 _NEW_PROGRAM_CONSTANTS | _NEW_POLYGON),
 182       .brw   = (BRW_NEW_CURBE_OFFSETS |
 183                 BRW_NEW_FRAGMENT_PROGRAM |
 184                 BRW_NEW_NR_WM_SURFACES |
 185                 BRW_NEW_URB_FENCE |
 186                 BRW_NEW_BATCH),
 187       .cache = (CACHE_NEW_SAMPLER |
 188                 CACHE_NEW_WM_PROG)
 189    },
 190    .emit = upload_wm_state,
 191 };