src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/program.h"
  34 #include "program/prog_parameter.h"
  35 #include "program/prog_statevars.h"
  36 #include "intel_batchbuffer.h"
  37
  38 static void
  39 gen6_upload_wm_push_constants(struct brw_context *brw)
  40 {
  41    struct brw_stage_state *stage_state = &brw->wm.base;
  42    /* BRW_NEW_FRAGMENT_PROGRAM */
  43    const struct brw_fragment_program *fp =
  44       brw_fragment_program_const(brw->fragment_program);
  45    /* CACHE_NEW_WM_PROG */
  46    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  47
  48    gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base,
  49                               stage_state, AUB_TRACE_WM_CONSTANTS);
  50
  51    if (brw->gen >= 7) {
  52       gen7_upload_constant_state(brw, &brw->wm.base, true,
  53                                  _3DSTATE_CONSTANT_PS);
  54    }
  55 }
  56
  57 const struct brw_tracked_state gen6_wm_push_constants = {
  58    .dirty = {
  59       .mesa  = _NEW_PROGRAM_CONSTANTS,
  60       .brw   = (BRW_NEW_BATCH |
  61                 BRW_NEW_FRAGMENT_PROGRAM |
  62                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
  63       .cache = CACHE_NEW_WM_PROG,
  64    },
  65    .emit = gen6_upload_wm_push_constants,
  66 };
  67
  68 static void
  69 upload_wm_state(struct brw_context *brw)
  70 {
  71    struct gl_context *ctx = &brw->ctx;
  72    const struct brw_fragment_program *fp =
  73       brw_fragment_program_const(brw->fragment_program);
  74    uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
  75
  76    /* _NEW_BUFFERS */
  77    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
  78
  79    /* CACHE_NEW_WM_PROG
  80     *
  81     * We can't fold this into gen6_upload_wm_push_constants(), because
  82     * according to the SNB PRM, vol 2 part 1 section 7.2.2
  83     * (3DSTATE_CONSTANT_PS [DevSNB]):
  84     *
  85     *     "[DevSNB]: This packet must be followed by WM_STATE."
  86     */
  87    if (brw->wm.prog_data->base.nr_params == 0) {
  88       /* Disable the push constant buffers. */
  89       BEGIN_BATCH(5);
  90       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
  91       OUT_BATCH(0);
  92       OUT_BATCH(0);
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95       ADVANCE_BATCH();
  96    } else {
  97       BEGIN_BATCH(5);
  98       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
  99                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 100                 (5 - 2));
 101       /* Pointer to the WM constant buffer.  Covered by the set of
 102        * state flags from gen6_upload_wm_push_constants.
 103        */
 104       OUT_BATCH(brw->wm.base.push_const_offset +
 105                 brw->wm.base.push_const_size - 1);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       ADVANCE_BATCH();
 110    }
 111
 112    dw2 = dw4 = dw5 = dw6 = ksp2 = 0;
 113    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 114    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 115    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 116
 117    /* Use ALT floating point mode for ARB fragment programs, because they
 118     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 119     * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
 120     * to differentiate between the GLSL and non-GLSL cases.
 121     */
 122    if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 123       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 124
 125    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
 126            GEN6_WM_SAMPLER_COUNT_SHIFT;
 127
 128    /* CACHE_NEW_WM_PROG */
 129    dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
 130            GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 131
 132    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 133
 134    /* CACHE_NEW_WM_PROG */
 135
 136    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 137     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 138     * is successfully compiled. In majority of the cases that bring us
 139     * better performance than 'SIMD8 only' dispatch.
 140     */
 141    int min_inv_per_frag =
 142       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
 143    assert(min_inv_per_frag >= 1);
 144
 145    if (brw->wm.prog_data->prog_offset_16) {
 146       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 147
 148       if (min_inv_per_frag == 1) {
 149          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 150          dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
 151                  GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 152          dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
 153                  GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 154          ksp0 = brw->wm.base.prog_offset;
 155          ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
 156       } else {
 157          dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
 158                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 159          ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
 160       }
 161    }
 162    else {
 163       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 164       dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
 165               GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 166       ksp0 = brw->wm.base.prog_offset;
 167    }
 168
 169    /* CACHE_NEW_WM_PROG | _NEW_COLOR */
 170    if (brw->wm.prog_data->dual_src_blend &&
 171        (ctx->Color.BlendEnabled & 1) &&
 172        ctx->Color.Blend[0]._UsesDualSrc) {
 173       dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
 174    }
 175
 176    /* _NEW_LINE */
 177    if (ctx->Line.StippleFlag)
 178       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 179
 180    /* _NEW_POLYGON */
 181    if (ctx->Polygon.StippleFlag)
 182       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 183
 184    /* BRW_NEW_FRAGMENT_PROGRAM */
 185    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
 186       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 187    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 188       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 189    /* CACHE_NEW_WM_PROG */
 190    dw6 |= brw->wm.prog_data->barycentric_interp_modes <<
 191       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 192
 193    /* _NEW_COLOR, _NEW_MULTISAMPLE */
 194    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
 195        ctx->Multisample.SampleAlphaToCoverage ||
 196        brw->wm.prog_data->uses_omask)
 197       dw5 |= GEN6_WM_KILL_ENABLE;
 198
 199    /* _NEW_BUFFERS | _NEW_COLOR */
 200    if (brw_color_buffer_write_enabled(brw) ||
 201        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 202       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 203    }
 204
 205    /* From the SNB PRM, volume 2 part 1, page 278:
 206     * "This bit is inserted in the PS payload header and made available to
 207     * the DataPort (either via the message header or via header bypass) to
 208     * indicate that oMask data (one or two phases) is included in Render
 209     * Target Write messages. If present, the oMask data is used to mask off
 210     * samples."
 211     */
 212     if(brw->wm.prog_data->uses_omask)
 213       dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
 214
 215    /* CACHE_NEW_WM_PROG */
 216    dw6 |= brw->wm.prog_data->num_varying_inputs <<
 217       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 218    if (multisampled_fbo) {
 219       /* _NEW_MULTISAMPLE */
 220       if (ctx->Multisample.Enabled)
 221          dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 222       else
 223          dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 224
 225       if (min_inv_per_frag > 1)
 226          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 227       else {
 228          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 229
 230          /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping
 231           * (Dispatch Size) Control"), p.334:
 232           *
 233           *     Note: in the table below, the Valid column indicates which
 234           *     products that combination is supported on. Combinations of
 235           *     dispatch enables not listed in the table are not available on
 236           *     any product.
 237           *
 238           *     A: Valid on all products
 239           *
 240           *     B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 241           *     computed depth.
 242           *
 243           *     D: Valid on all products, except when in non-1x PERSAMPLE mode
 244           *     (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x
 245           *     PERPIXEL mode with pixel shader computed depth.
 246           *
 247           *     E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 248           *     computed depth.
 249           *
 250           *     F: Valid on all products, except not valid on [DevSNB] if 4x
 251           *     PERPIXEL mode with pixel shader computed depth.
 252           *
 253           * In the table that follows, the only entry with "A" in the Valid
 254           * column is the entry where only 8 pixel dispatch is enabled.
 255           * Therefore, when we are in PERPIXEL mode with pixel shader computed
 256           * depth, we need to disable SIMD16 dispatch.
 257           */
 258          if (dw5 & GEN6_WM_COMPUTED_DEPTH)
 259             dw5 &= ~GEN6_WM_16_DISPATCH_ENABLE;
 260       }
 261    } else {
 262       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 263       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 264    }
 265
 266    /* From the SNB PRM, volume 2 part 1, page 281:
 267     * "If the PS kernel does not need the Position XY Offsets
 268     * to compute a Position XY value, then this field should be
 269     * programmed to POSOFFSET_NONE."
 270     *
 271     * "SW Recommendation: If the PS kernel needs the Position Offsets
 272     * to compute a Position XY value, this field should match Position
 273     * ZW Interpolation Mode to ensure a consistent position.xyzw
 274     * computation."
 275     * We only require XY sample offsets. So, this recommendation doesn't
 276     * look useful at the moment. We might need this in future.
 277     */
 278    if (brw->wm.prog_data->uses_pos_offset)
 279       dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
 280    else
 281       dw6 |= GEN6_WM_POSOFFSET_NONE;
 282
 283    BEGIN_BATCH(9);
 284    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 285    OUT_BATCH(ksp0);
 286    OUT_BATCH(dw2);
 287    if (brw->wm.prog_data->total_scratch) {
 288       OUT_RELOC(brw->wm.base.scratch_bo,
 289                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 290                 ffs(brw->wm.prog_data->total_scratch) - 11);
 291    } else {
 292       OUT_BATCH(0);
 293    }
 294    OUT_BATCH(dw4);
 295    OUT_BATCH(dw5);
 296    OUT_BATCH(dw6);
 297    OUT_BATCH(0); /* kernel 1 pointer */
 298    OUT_BATCH(ksp2);
 299    ADVANCE_BATCH();
 300 }
 301
 302 const struct brw_tracked_state gen6_wm_state = {
 303    .dirty = {
 304       .mesa  = (_NEW_LINE |
 305                 _NEW_COLOR |
 306                 _NEW_BUFFERS |
 307                 _NEW_PROGRAM_CONSTANTS |
 308                 _NEW_POLYGON |
 309                 _NEW_MULTISAMPLE),
 310       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 311                 BRW_NEW_BATCH |
 312                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 313       .cache = (CACHE_NEW_WM_PROG)
 314    },
 315    .emit = upload_wm_state,
 316 };