src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/prog_parameter.h"
  34 #include "program/prog_statevars.h"
  35 #include "intel_batchbuffer.h"
  36
  37 static void
  38 gen6_upload_wm_push_constants(struct brw_context *brw)
  39 {
  40    struct gl_context *ctx = &brw->ctx;
  41    /* BRW_NEW_FRAGMENT_PROGRAM */
  42    const struct brw_fragment_program *fp =
  43       brw_fragment_program_const(brw->fragment_program);
  44
  45    /* Updates the ParameterValues[i] pointers for all parameters of the
  46     * basic type of PROGRAM_STATE_VAR.
  47     */
  48    /* XXX: Should this happen somewhere before to get our state flag set? */
  49    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  50
  51    /* CACHE_NEW_WM_PROG */
  52    if (brw->wm.prog_data->nr_params != 0) {
  53       float *constants;
  54       unsigned int i;
  55
  56       constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
  57                                   brw->wm.prog_data->nr_params *
  58                                   sizeof(float),
  59                                   32, &brw->wm.base.push_const_offset);
  60
  61       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  62          constants[i] = *brw->wm.prog_data->param[i];
  63       }
  64
  65       if (0) {
  66          printf("WM constants:\n");
  67          for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  68             if ((i & 7) == 0)
  69                printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
  70             printf("%8f ", constants[i]);
  71             if ((i & 7) == 7)
  72                printf("\n");
  73          }
  74          if ((i & 7) != 0)
  75             printf("\n");
  76          printf("\n");
  77       }
  78    }
  79 }
  80
  81 const struct brw_tracked_state gen6_wm_push_constants = {
  82    .dirty = {
  83       .mesa  = _NEW_PROGRAM_CONSTANTS,
  84       .brw   = (BRW_NEW_BATCH |
  85                 BRW_NEW_FRAGMENT_PROGRAM),
  86       .cache = CACHE_NEW_WM_PROG,
  87    },
  88    .emit = gen6_upload_wm_push_constants,
  89 };
  90
  91 static void
  92 upload_wm_state(struct brw_context *brw)
  93 {
  94    struct gl_context *ctx = &brw->ctx;
  95    const struct brw_fragment_program *fp =
  96       brw_fragment_program_const(brw->fragment_program);
  97    uint32_t dw2, dw4, dw5, dw6;
  98
  99    /* _NEW_BUFFERS */
 100    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
 101
 102     /* CACHE_NEW_WM_PROG */
 103    if (brw->wm.prog_data->nr_params == 0) {
 104       /* Disable the push constant buffers. */
 105       BEGIN_BATCH(5);
 106       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       OUT_BATCH(0);
 111       ADVANCE_BATCH();
 112    } else {
 113       BEGIN_BATCH(5);
 114       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 115                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 116                 (5 - 2));
 117       /* Pointer to the WM constant buffer.  Covered by the set of
 118        * state flags from gen6_upload_wm_push_constants.
 119        */
 120       OUT_BATCH(brw->wm.base.push_const_offset +
 121                 ALIGN(brw->wm.prog_data->nr_params,
 122                       brw->wm.prog_data->dispatch_width) / 8 - 1);
 123       OUT_BATCH(0);
 124       OUT_BATCH(0);
 125       OUT_BATCH(0);
 126       ADVANCE_BATCH();
 127    }
 128
 129    dw2 = dw4 = dw5 = dw6 = 0;
 130    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 131    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 132    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 133
 134    /* Use ALT floating point mode for ARB fragment programs, because they
 135     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 136     * rendering, CurrentFragmentProgram is used for this check to
 137     * differentiate between the GLSL and non-GLSL cases.
 138     */
 139    if (ctx->Shader.CurrentFragmentProgram == NULL)
 140       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 141
 142    /* CACHE_NEW_SAMPLER */
 143    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
 144            GEN6_WM_SAMPLER_COUNT_SHIFT;
 145    dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 146            GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 147    dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 148            GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 149
 150    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 151
 152    /* CACHE_NEW_WM_PROG */
 153    dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 154    if (brw->wm.prog_data->prog_offset_16)
 155       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 156
 157    /* CACHE_NEW_WM_PROG | _NEW_COLOR */
 158    if (brw->wm.prog_data->dual_src_blend &&
 159        (ctx->Color.BlendEnabled & 1) &&
 160        ctx->Color.Blend[0]._UsesDualSrc) {
 161       dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
 162    }
 163
 164    /* _NEW_LINE */
 165    if (ctx->Line.StippleFlag)
 166       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 167
 168    /* _NEW_POLYGON */
 169    if (ctx->Polygon.StippleFlag)
 170       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 171
 172    /* BRW_NEW_FRAGMENT_PROGRAM */
 173    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
 174       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 175    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 176       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 177    /* CACHE_NEW_WM_PROG */
 178    dw6 |= brw->wm.prog_data->barycentric_interp_modes <<
 179       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 180
 181    /* _NEW_COLOR, _NEW_MULTISAMPLE */
 182    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
 183        ctx->Multisample.SampleAlphaToCoverage)
 184       dw5 |= GEN6_WM_KILL_ENABLE;
 185
 186    if (brw_color_buffer_write_enabled(brw) ||
 187        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 188       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 189    }
 190
 191    dw6 |= _mesa_bitcount_64(brw->fragment_program->Base.InputsRead) <<
 192       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 193    if (multisampled_fbo) {
 194       /* _NEW_MULTISAMPLE */
 195       if (ctx->Multisample.Enabled)
 196          dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 197       else
 198          dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 199       dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 200    } else {
 201       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 202       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 203    }
 204
 205    BEGIN_BATCH(9);
 206    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 207    OUT_BATCH(brw->wm.base.prog_offset);
 208    OUT_BATCH(dw2);
 209    if (brw->wm.prog_data->total_scratch) {
 210       OUT_RELOC(brw->wm.base.scratch_bo,
 211                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 212                 ffs(brw->wm.prog_data->total_scratch) - 11);
 213    } else {
 214       OUT_BATCH(0);
 215    }
 216    OUT_BATCH(dw4);
 217    OUT_BATCH(dw5);
 218    OUT_BATCH(dw6);
 219    OUT_BATCH(0); /* kernel 1 pointer */
 220    /* kernel 2 pointer */
 221    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 222    ADVANCE_BATCH();
 223 }
 224
 225 const struct brw_tracked_state gen6_wm_state = {
 226    .dirty = {
 227       .mesa  = (_NEW_LINE |
 228                 _NEW_COLOR |
 229                 _NEW_BUFFERS |
 230                 _NEW_PROGRAM_CONSTANTS |
 231                 _NEW_POLYGON |
 232                 _NEW_MULTISAMPLE),
 233       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 234                 BRW_NEW_BATCH |
 235                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 236       .cache = (CACHE_NEW_SAMPLER |
 237                 CACHE_NEW_WM_PROG)
 238    },
 239    .emit = upload_wm_state,
 240 };