src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/prog_parameter.h"
  34 #include "program/prog_statevars.h"
  35 #include "intel_batchbuffer.h"
  36
  37 static void
  38 gen6_prepare_wm_push_constants(struct brw_context *brw)
  39 {
  40    struct intel_context *intel = &brw->intel;
  41    struct gl_context *ctx = &intel->ctx;
  42    const struct brw_fragment_program *fp =
  43       brw_fragment_program_const(brw->fragment_program);
  44
  45    /* Updates the ParameterValues[i] pointers for all parameters of the
  46     * basic type of PROGRAM_STATE_VAR.
  47     */
  48    /* XXX: Should this happen somewhere before to get our state flag set? */
  49    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  50
  51    if (brw->wm.prog_data->nr_params != 0) {
  52       float *constants;
  53       unsigned int i;
  54
  55       constants = brw_state_batch(brw,
  56                                   brw->wm.prog_data->nr_params *
  57                                   sizeof(float),
  58                                   32, &brw->wm.push_const_offset);
  59
  60       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  61          constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
  62                                       *brw->wm.prog_data->param[i]);
  63       }
  64
  65       if (0) {
  66          printf("WM constants:\n");
  67          for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  68             if ((i & 7) == 0)
  69                printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
  70             printf("%8f ", constants[i]);
  71             if ((i & 7) == 7)
  72                printf("\n");
  73          }
  74          if ((i & 7) != 0)
  75             printf("\n");
  76          printf("\n");
  77       }
  78    }
  79 }
  80
  81 const struct brw_tracked_state gen6_wm_constants = {
  82    .dirty = {
  83       .mesa  = _NEW_PROGRAM_CONSTANTS,
  84       .brw   = (BRW_NEW_BATCH |
  85                 BRW_NEW_FRAGMENT_PROGRAM),
  86       .cache = 0,
  87    },
  88    .prepare = gen6_prepare_wm_push_constants,
  89 };
  90
  91 static void
  92 upload_wm_state(struct brw_context *brw)
  93 {
  94    struct intel_context *intel = &brw->intel;
  95    struct gl_context *ctx = &intel->ctx;
  96    const struct brw_fragment_program *fp =
  97       brw_fragment_program_const(brw->fragment_program);
  98    uint32_t dw2, dw4, dw5, dw6;
  99
 100    /* CACHE_NEW_WM_PROG */
 101    if (brw->wm.prog_data->nr_params == 0) {
 102       /* Disable the push constant buffers. */
 103       BEGIN_BATCH(5);
 104       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       ADVANCE_BATCH();
 110    } else {
 111       BEGIN_BATCH(5);
 112       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 113                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 114                 (5 - 2));
 115       /* Pointer to the WM constant buffer.  Covered by the set of
 116        * state flags from gen6_prepare_wm_constants
 117        */
 118       OUT_BATCH(brw->wm.push_const_offset +
 119                 ALIGN(brw->wm.prog_data->nr_params,
 120                       brw->wm.prog_data->dispatch_width) / 8 - 1);
 121       OUT_BATCH(0);
 122       OUT_BATCH(0);
 123       OUT_BATCH(0);
 124       ADVANCE_BATCH();
 125    }
 126
 127    dw2 = dw4 = dw5 = dw6 = 0;
 128    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 129    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 130    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 131
 132    /* OpenGL non-ieee floating point mode */
 133    dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 134
 135    /* BRW_NEW_NR_WM_SURFACES */
 136    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 137
 138    /* CACHE_NEW_SAMPLER */
 139    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
 140    dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 141            GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 142    dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 143            GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 144
 145    dw5 |= (brw->wm_max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 146
 147    /* CACHE_NEW_WM_PROG */
 148    if (brw->wm.prog_data->dispatch_width == 8) {
 149       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 150       if (brw->wm.prog_data->prog_offset_16)
 151          dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 152    } else {
 153       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 154    }
 155
 156    /* _NEW_LINE */
 157    if (ctx->Line.StippleFlag)
 158       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 159
 160    /* _NEW_POLYGONSTIPPLE */
 161    if (ctx->Polygon.StippleFlag)
 162       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 163
 164    /* BRW_NEW_FRAGMENT_PROGRAM */
 165    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 166       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 167    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 168       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 169
 170    /* _NEW_COLOR */
 171    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
 172       dw5 |= GEN6_WM_KILL_ENABLE;
 173
 174    if (brw_color_buffer_write_enabled(brw) ||
 175        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 176       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 177    }
 178
 179    dw6 |= GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 180
 181    dw6 |= brw_count_bits(brw->fragment_program->Base.InputsRead) <<
 182       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 183
 184    BEGIN_BATCH(9);
 185    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 186    OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 187    OUT_BATCH(dw2);
 188    if (brw->wm.prog_data->total_scratch) {
 189       OUT_RELOC(brw->wm.scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 190                 ffs(brw->wm.prog_data->total_scratch) - 11);
 191    } else {
 192       OUT_BATCH(0);
 193    }
 194    OUT_BATCH(dw4);
 195    OUT_BATCH(dw5);
 196    OUT_BATCH(dw6);
 197    OUT_BATCH(0); /* kernel 1 pointer */
 198    if (brw->wm.prog_data->prog_offset_16) {
 199       OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 200                 brw->wm.prog_data->prog_offset_16);
 201    } else {
 202       OUT_BATCH(0); /* kernel 2 pointer */
 203    }
 204    ADVANCE_BATCH();
 205 }
 206
 207 const struct brw_tracked_state gen6_wm_state = {
 208    .dirty = {
 209       .mesa  = (_NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR | _NEW_BUFFERS |
 210                 _NEW_PROGRAM_CONSTANTS | _NEW_POLYGON),
 211       .brw   = (BRW_NEW_CURBE_OFFSETS |
 212                 BRW_NEW_FRAGMENT_PROGRAM |
 213                 BRW_NEW_NR_WM_SURFACES |
 214                 BRW_NEW_URB_FENCE |
 215                 BRW_NEW_BATCH),
 216       .cache = (CACHE_NEW_SAMPLER |
 217                 CACHE_NEW_WM_PROG)
 218    },
 219    .emit = upload_wm_state,
 220 };