src/mesa/drivers/dri/i965/gen7_blorp.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "brw_blorp.h"
  33
  34 static bool
  35 gen7_blorp_skip_urb_config(const struct brw_context *brw)
  36 {
  37    if (brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE))
  38       return false;
  39
  40    /* Vertex buffer takes 24 bytes. As the size is expressed in 64 bytes,
  41     * one will suffice, otherwise the setup can be any valid configuration.
  42     */
  43    return brw->urb.vsize > 0;
  44 }
  45
  46 /* 3DSTATE_URB_VS
  47  * 3DSTATE_URB_HS
  48  * 3DSTATE_URB_DS
  49  * 3DSTATE_URB_GS
  50  *
  51  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  52  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  53  *
  54  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  55  *     programmed in order for the programming of this state to be
  56  *     valid.
  57  */
  58 void
  59 gen7_blorp_emit_urb_config(struct brw_context *brw)
  60 {
  61    /* URB allocations must be done in 8k chunks. */
  62    const unsigned chunk_size_bytes = 8192;
  63    const unsigned urb_size =
  64       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
  65    const unsigned push_constant_bytes = 1024 * urb_size;
  66    const unsigned push_constant_chunks =
  67       push_constant_bytes / chunk_size_bytes;
  68    const unsigned vs_size = 1;
  69    const unsigned vs_start = push_constant_chunks;
  70    const unsigned vs_chunks =
  71       DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes);
  72
  73    if (gen7_blorp_skip_urb_config(brw))
  74       return;
  75
  76    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
  77
  78    gen7_emit_push_constant_state(brw,
  79                                  urb_size / 2 /* vs_size */,
  80                                  0 /* hs_size */,
  81                                  0 /* ds_size */,
  82                                  0 /* gs_size */,
  83                                  urb_size / 2 /* fs_size */);
  84
  85    gen7_emit_urb_state(brw,
  86                        brw->urb.min_vs_entries /* num_vs_entries */,
  87                        vs_size,
  88                        vs_start,
  89                        0 /* num_hs_entries */,
  90                        1 /* hs_size */,
  91                        vs_start + vs_chunks /* hs_start */,
  92                        0 /* num_ds_entries */,
  93                        1 /* ds_size */,
  94                        vs_start + vs_chunks /* ds_start */,
  95                        0 /* num_gs_entries */,
  96                        1 /* gs_size */,
  97                        vs_start + vs_chunks /* gs_start */);
  98 }
  99
 100
 101 /* 3DSTATE_BLEND_STATE_POINTERS */
 102 void
 103 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 104                                     uint32_t cc_blend_state_offset)
 105 {
 106    BEGIN_BATCH(2);
 107    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
 108    OUT_BATCH(cc_blend_state_offset | 1);
 109    ADVANCE_BATCH();
 110 }
 111
 112
 113 /* 3DSTATE_CC_STATE_POINTERS */
 114 void
 115 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 116                                  uint32_t cc_state_offset)
 117 {
 118    BEGIN_BATCH(2);
 119    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 120    OUT_BATCH(cc_state_offset | 1);
 121    ADVANCE_BATCH();
 122 }
 123
 124 void
 125 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 126 {
 127    struct brw_cc_viewport *ccv;
 128    uint32_t cc_vp_offset;
 129
 130    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 131                                                    sizeof(*ccv), 32,
 132                                                    &cc_vp_offset);
 133    ccv->min_depth = 0.0;
 134    ccv->max_depth = 1.0;
 135
 136    BEGIN_BATCH(2);
 137    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 138    OUT_BATCH(cc_vp_offset);
 139    ADVANCE_BATCH();
 140 }
 141
 142
 143 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 144  *
 145  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 146  */
 147 static void
 148 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 149                                              uint32_t depthstencil_offset)
 150 {
 151    BEGIN_BATCH(2);
 152    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 153    OUT_BATCH(depthstencil_offset | 1);
 154    ADVANCE_BATCH();
 155 }
 156
 157
 158 /* SURFACE_STATE for renderbuffer or texture surface (see
 159  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 160  */
 161 static uint32_t
 162 gen7_blorp_emit_surface_state(struct brw_context *brw,
 163                               const struct brw_blorp_surface_info *surface,
 164                               uint32_t read_domains, uint32_t write_domain,
 165                               bool is_render_target)
 166 {
 167    uint32_t wm_surf_offset;
 168    uint32_t width = surface->width;
 169    uint32_t height = surface->height;
 170    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 171     * color surfaces, width and height are measured in pixels; we don't need
 172     * to divide them by 2 as we do for Gen6 (see
 173     * gen6_blorp_emit_surface_state).
 174     */
 175    struct intel_mipmap_tree *mt = surface->mt;
 176    uint32_t tile_x, tile_y;
 177    const uint8_t mocs = GEN7_MOCS_L3;
 178
 179    uint32_t tiling = surface->map_stencil_as_y_tiled
 180       ? I915_TILING_Y : mt->tiling;
 181
 182    uint32_t *surf = (uint32_t *)
 183       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 184    memset(surf, 0, 8 * 4);
 185
 186    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 187              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 188              gen7_surface_tiling_mode(tiling);
 189
 190    if (surface->mt->valign == 4)
 191       surf[0] |= GEN7_SURFACE_VALIGN_4;
 192    if (surface->mt->halign == 8)
 193       surf[0] |= GEN7_SURFACE_HALIGN_8;
 194
 195    if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
 196       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 197    else
 198       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 199
 200    /* reloc */
 201    surf[1] = brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y) +
 202              mt->bo->offset64;
 203
 204    /* Note that the low bits of these fields are missing, so
 205     * there's the possibility of getting in trouble.
 206     */
 207    assert(tile_x % 4 == 0);
 208    assert(tile_y % 2 == 0);
 209    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 210              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 211              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 212
 213    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 214              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 215
 216    uint32_t pitch_bytes = mt->pitch;
 217    if (surface->map_stencil_as_y_tiled)
 218       pitch_bytes *= 2;
 219    surf[3] = pitch_bytes - 1;
 220
 221    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 222    if (surface->mt->mcs_mt) {
 223       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 224                                 is_render_target);
 225    }
 226
 227    surf[7] = surface->mt->fast_clear_color_value;
 228
 229    if (brw->is_haswell) {
 230       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 231                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 232                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 233                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 234    }
 235
 236    /* Emit relocation to surface contents */
 237    drm_intel_bo_emit_reloc(brw->batch.bo,
 238                            wm_surf_offset + 4,
 239                            mt->bo,
 240                            surf[1] - mt->bo->offset64,
 241                            read_domains, write_domain);
 242
 243    gen7_check_surface_setup(surf, is_render_target);
 244
 245    return wm_surf_offset;
 246 }
 247
 248
 249 /* 3DSTATE_VS
 250  *
 251  * Disable vertex shader.
 252  */
 253 static void
 254 gen7_blorp_emit_vs_disable(struct brw_context *brw)
 255 {
 256    BEGIN_BATCH(7);
 257    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 258    OUT_BATCH(0);
 259    OUT_BATCH(0);
 260    OUT_BATCH(0);
 261    OUT_BATCH(0);
 262    OUT_BATCH(0);
 263    OUT_BATCH(0);
 264    ADVANCE_BATCH();
 265
 266    BEGIN_BATCH(6);
 267    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 268    OUT_BATCH(0);
 269    OUT_BATCH(0);
 270    OUT_BATCH(0);
 271    OUT_BATCH(0);
 272    OUT_BATCH(0);
 273    ADVANCE_BATCH();
 274 }
 275
 276
 277 /* 3DSTATE_HS
 278  *
 279  * Disable the hull shader.
 280  */
 281 static void
 282 gen7_blorp_emit_hs_disable(struct brw_context *brw)
 283 {
 284    BEGIN_BATCH(7);
 285    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 286    OUT_BATCH(0);
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    OUT_BATCH(0);
 290    OUT_BATCH(0);
 291    OUT_BATCH(0);
 292    ADVANCE_BATCH();
 293
 294    BEGIN_BATCH(7);
 295    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    OUT_BATCH(0);
 300    OUT_BATCH(0);
 301    OUT_BATCH(0);
 302    ADVANCE_BATCH();
 303 }
 304
 305
 306 /* 3DSTATE_TE
 307  *
 308  * Disable the tesselation engine.
 309  */
 310 void
 311 gen7_blorp_emit_te_disable(struct brw_context *brw)
 312 {
 313    BEGIN_BATCH(4);
 314    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    ADVANCE_BATCH();
 319 }
 320
 321
 322 /* 3DSTATE_DS
 323  *
 324  * Disable the domain shader.
 325  */
 326 static void
 327 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 328 {
 329    BEGIN_BATCH(7);
 330    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 331    OUT_BATCH(0);
 332    OUT_BATCH(0);
 333    OUT_BATCH(0);
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    OUT_BATCH(0);
 337    ADVANCE_BATCH();
 338
 339    BEGIN_BATCH(6);
 340    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 341    OUT_BATCH(0);
 342    OUT_BATCH(0);
 343    OUT_BATCH(0);
 344    OUT_BATCH(0);
 345    OUT_BATCH(0);
 346    ADVANCE_BATCH();
 347 }
 348
 349 /* 3DSTATE_GS
 350  *
 351  * Disable the geometry shader.
 352  */
 353 static void
 354 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 355 {
 356    BEGIN_BATCH(7);
 357    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 358    OUT_BATCH(0);
 359    OUT_BATCH(0);
 360    OUT_BATCH(0);
 361    OUT_BATCH(0);
 362    OUT_BATCH(0);
 363    OUT_BATCH(0);
 364    ADVANCE_BATCH();
 365
 366    /**
 367     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 368     * Geometry > Geometry Shader > State:
 369     *
 370     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 371     *     whole fixed function pipeline when the GS enable changes value in
 372     *     the 3DSTATE_GS."
 373     *
 374     * The hardware architects have clarified that in this context "flush the
 375     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 376     * Stall" bit set.
 377     */
 378    if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 379       gen7_emit_cs_stall_flush(brw);
 380
 381    BEGIN_BATCH(7);
 382    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 383    OUT_BATCH(0);
 384    OUT_BATCH(0);
 385    OUT_BATCH(0);
 386    OUT_BATCH(0);
 387    OUT_BATCH(0);
 388    OUT_BATCH(0);
 389    ADVANCE_BATCH();
 390    brw->gs.enabled = false;
 391 }
 392
 393 /* 3DSTATE_STREAMOUT
 394  *
 395  * Disable streamout.
 396  */
 397 static void
 398 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 399 {
 400    BEGIN_BATCH(3);
 401    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 402    OUT_BATCH(0);
 403    OUT_BATCH(0);
 404    ADVANCE_BATCH();
 405 }
 406
 407
 408 static void
 409 gen7_blorp_emit_sf_config(struct brw_context *brw,
 410                           const struct brw_blorp_params *params)
 411 {
 412    /* 3DSTATE_SF
 413     *
 414     * Disable ViewportTransformEnable (dw1.1)
 415     *
 416     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 417     * Primitives Overview":
 418     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 419     *     use of screen- space coordinates).
 420     *
 421     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 422     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 423     *
 424     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 425     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 426     *     SOLID: Any triangle or rectangle object found to be front-facing
 427     *     is rendered as a solid object. This setting is required when
 428     *     (rendering rectangle (RECTLIST) objects.
 429     */
 430    {
 431       BEGIN_BATCH(7);
 432       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 433       OUT_BATCH(params->depth_format <<
 434                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 435       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 436       OUT_BATCH(0);
 437       OUT_BATCH(0);
 438       OUT_BATCH(0);
 439       OUT_BATCH(0);
 440       ADVANCE_BATCH();
 441    }
 442
 443    /* 3DSTATE_SBE */
 444    {
 445       BEGIN_BATCH(14);
 446       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 447       OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
 448                 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 449                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 450                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 451                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 452       for (int i = 0; i < 12; ++i)
 453          OUT_BATCH(0);
 454       ADVANCE_BATCH();
 455    }
 456 }
 457
 458
 459 /**
 460  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 461  */
 462 static void
 463 gen7_blorp_emit_wm_config(struct brw_context *brw,
 464                           const struct brw_blorp_params *params)
 465 {
 466    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 467    uint32_t dw1 = 0, dw2 = 0;
 468
 469    switch (params->hiz_op) {
 470    case GEN6_HIZ_OP_DEPTH_CLEAR:
 471       dw1 |= GEN7_WM_DEPTH_CLEAR;
 472       break;
 473    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 474       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 475       break;
 476    case GEN6_HIZ_OP_HIZ_RESOLVE:
 477       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 478       break;
 479    case GEN6_HIZ_OP_NONE:
 480       break;
 481    default:
 482       unreachable("not reached");
 483    }
 484    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 485    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 486    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 487
 488    if (params->wm_prog_data)
 489       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 490
 491    if (params->src.mt)
 492       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 493
 494    if (params->dst.num_samples > 1) {
 495       dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 496       if (prog_data && prog_data->persample_msaa_dispatch)
 497          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 498       else
 499          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 500    } else {
 501       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 502       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 503    }
 504
 505    BEGIN_BATCH(3);
 506    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 507    OUT_BATCH(dw1);
 508    OUT_BATCH(dw2);
 509    ADVANCE_BATCH();
 510 }
 511
 512
 513 /**
 514  * 3DSTATE_PS
 515  *
 516  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 517  * that, thread dispatch info must still be specified.
 518  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 519  *       valid range for this field is [0x3, 0x2f].
 520  *     - A dispatch mode must be given; that is, at least one of the
 521  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 522  *       discovered through simulator error messages.
 523  */
 524 static void
 525 gen7_blorp_emit_ps_config(struct brw_context *brw,
 526                           const struct brw_blorp_params *params)
 527 {
 528    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 529    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 530    const int max_threads_shift = brw->is_haswell ?
 531       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 532
 533    dw2 = dw4 = dw5 = ksp0 = ksp2 = 0;
 534    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 535
 536    if (brw->is_haswell)
 537       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 538    if (params->wm_prog_data) {
 539       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 540
 541       dw5 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 542       dw5 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 543
 544       ksp0 = params->wm_prog_kernel;
 545       ksp2 = params->wm_prog_kernel + params->wm_prog_data->ksp_offset_2;
 546
 547       if (params->wm_prog_data->dispatch_8)
 548          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 549       if (params->wm_prog_data->dispatch_16)
 550          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 551    } else {
 552       /* The hardware gets angry if we don't enable at least one dispatch
 553        * mode, so just enable 16-pixel dispatch if we don't have a program.
 554        */
 555       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 556    }
 557
 558    if (params->src.mt)
 559       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 560
 561    dw4 |= params->fast_clear_op;
 562
 563    BEGIN_BATCH(8);
 564    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 565    OUT_BATCH(ksp0);
 566    OUT_BATCH(dw2);
 567    OUT_BATCH(0);
 568    OUT_BATCH(dw4);
 569    OUT_BATCH(dw5);
 570    OUT_BATCH(0); /* kernel 1 pointer */
 571    OUT_BATCH(ksp2);
 572    ADVANCE_BATCH();
 573 }
 574
 575
 576 void
 577 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 578                                           uint32_t wm_bind_bo_offset)
 579 {
 580    BEGIN_BATCH(2);
 581    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 582    OUT_BATCH(wm_bind_bo_offset);
 583    ADVANCE_BATCH();
 584 }
 585
 586
 587 void
 588 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 589                                           uint32_t sampler_offset)
 590 {
 591    BEGIN_BATCH(2);
 592    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 593    OUT_BATCH(sampler_offset);
 594    ADVANCE_BATCH();
 595 }
 596
 597
 598 void
 599 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 600                             uint32_t wm_push_const_offset)
 601 {
 602    const uint8_t mocs = GEN7_MOCS_L3;
 603
 604    /* Make sure the push constants fill an exact integer number of
 605     * registers.
 606     */
 607    assert(sizeof(struct brw_blorp_wm_push_constants) % 32 == 0);
 608
 609    /* There must be at least one register worth of push constant data. */
 610    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 611
 612    /* Enable push constant buffer 0. */
 613    BEGIN_BATCH(7);
 614    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 615              (7 - 2));
 616    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 617    OUT_BATCH(0);
 618    OUT_BATCH(wm_push_const_offset | mocs);
 619    OUT_BATCH(0);
 620    OUT_BATCH(0);
 621    OUT_BATCH(0);
 622    ADVANCE_BATCH();
 623 }
 624
 625 void
 626 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 627 {
 628    BEGIN_BATCH(7);
 629    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 630    OUT_BATCH(0);
 631    OUT_BATCH(0);
 632    OUT_BATCH(0);
 633    OUT_BATCH(0);
 634    OUT_BATCH(0);
 635    OUT_BATCH(0);
 636    ADVANCE_BATCH();
 637 }
 638
 639 static void
 640 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 641                                      const struct brw_blorp_params *params)
 642 {
 643    const uint8_t mocs = GEN7_MOCS_L3;
 644    uint32_t surfwidth, surfheight;
 645    uint32_t surftype;
 646    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 647    unsigned int min_array_element;
 648    GLenum gl_target = params->depth.mt->target;
 649    unsigned int lod;
 650
 651    switch (gl_target) {
 652    case GL_TEXTURE_CUBE_MAP_ARRAY:
 653    case GL_TEXTURE_CUBE_MAP:
 654       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 655        * situation, but experiments show that gl_Layer doesn't work when we do
 656        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 657        * equivalent.
 658        */
 659       surftype = BRW_SURFACE_2D;
 660       depth *= 6;
 661       break;
 662    default:
 663       surftype = translate_tex_target(gl_target);
 664       break;
 665    }
 666
 667    min_array_element = params->depth.layer;
 668    if (params->depth.mt->num_samples > 1) {
 669       /* Convert physical layer to logical layer. */
 670       min_array_element /= params->depth.mt->num_samples;
 671    }
 672
 673    lod = params->depth.level - params->depth.mt->first_level;
 674
 675    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 676       /* HIZ ops for lod 0 may set the width & height a little
 677        * larger to allow the fast depth clear to fit the hardware
 678        * alignment requirements. (8x4)
 679        */
 680       surfwidth = params->depth.width;
 681       surfheight = params->depth.height;
 682    } else {
 683       surfwidth = params->depth.mt->logical_width0;
 684       surfheight = params->depth.mt->logical_height0;
 685    }
 686
 687    /* 3DSTATE_DEPTH_BUFFER */
 688    {
 689       brw_emit_depth_stall_flushes(brw);
 690
 691       BEGIN_BATCH(7);
 692       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 693       OUT_BATCH((params->depth.mt->pitch - 1) |
 694                 params->depth_format << 18 |
 695                 1 << 22 | /* hiz enable */
 696                 1 << 28 | /* depth write */
 697                 surftype << 29);
 698       OUT_RELOC(params->depth.mt->bo,
 699                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 700                 0);
 701       OUT_BATCH((surfwidth - 1) << 4 |
 702                 (surfheight - 1) << 18 |
 703                 lod);
 704       OUT_BATCH(((depth - 1) << 21) |
 705                 (min_array_element << 10) |
 706                 mocs);
 707       OUT_BATCH(0);
 708       OUT_BATCH((depth - 1) << 21);
 709       ADVANCE_BATCH();
 710    }
 711
 712    /* 3DSTATE_HIER_DEPTH_BUFFER */
 713    {
 714       struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 715
 716       BEGIN_BATCH(3);
 717       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 718       OUT_BATCH((mocs << 25) |
 719                 (hiz_buf->pitch - 1));
 720       OUT_RELOC(hiz_buf->bo,
 721                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 722                 0);
 723       ADVANCE_BATCH();
 724    }
 725
 726    /* 3DSTATE_STENCIL_BUFFER */
 727    {
 728       BEGIN_BATCH(3);
 729       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 730       OUT_BATCH(0);
 731       OUT_BATCH(0);
 732       ADVANCE_BATCH();
 733    }
 734 }
 735
 736
 737 static void
 738 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 739 {
 740    brw_emit_depth_stall_flushes(brw);
 741
 742    BEGIN_BATCH(7);
 743    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 744    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 745    OUT_BATCH(0);
 746    OUT_BATCH(0);
 747    OUT_BATCH(0);
 748    OUT_BATCH(0);
 749    OUT_BATCH(0);
 750    ADVANCE_BATCH();
 751
 752    BEGIN_BATCH(3);
 753    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 754    OUT_BATCH(0);
 755    OUT_BATCH(0);
 756    ADVANCE_BATCH();
 757
 758    BEGIN_BATCH(3);
 759    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 760    OUT_BATCH(0);
 761    OUT_BATCH(0);
 762    ADVANCE_BATCH();
 763 }
 764
 765
 766 /* 3DSTATE_CLEAR_PARAMS
 767  *
 768  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 769  * 3DSTATE_CLEAR_PARAMS:
 770  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 771  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 772  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 773  */
 774 void
 775 gen7_blorp_emit_clear_params(struct brw_context *brw,
 776                              const struct brw_blorp_params *params)
 777 {
 778    BEGIN_BATCH(3);
 779    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 780    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 781    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 782    ADVANCE_BATCH();
 783 }
 784
 785
 786 /* 3DPRIMITIVE */
 787 void
 788 gen7_blorp_emit_primitive(struct brw_context *brw,
 789                           const struct brw_blorp_params *params)
 790 {
 791    BEGIN_BATCH(7);
 792    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 793    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 794              _3DPRIM_RECTLIST);
 795    OUT_BATCH(3); /* vertex count per instance */
 796    OUT_BATCH(0);
 797    OUT_BATCH(params->num_layers); /* instance count */
 798    OUT_BATCH(0);
 799    OUT_BATCH(0);
 800    ADVANCE_BATCH();
 801 }
 802
 803
 804 /**
 805  * \copydoc gen6_blorp_exec()
 806  */
 807 void
 808 gen7_blorp_exec(struct brw_context *brw,
 809                 const struct brw_blorp_params *params)
 810 {
 811    if (brw->gen >= 8)
 812       return;
 813
 814    uint32_t cc_blend_state_offset = 0;
 815    uint32_t cc_state_offset = 0;
 816    uint32_t depthstencil_offset;
 817    uint32_t wm_push_const_offset = 0;
 818    uint32_t wm_bind_bo_offset = 0;
 819
 820    brw_upload_state_base_address(brw);
 821
 822    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 823    gen6_emit_3dstate_sample_mask(brw,
 824                                  params->dst.num_samples > 1 ?
 825                                  (1 << params->dst.num_samples) - 1 : 1);
 826    gen6_blorp_emit_vertices(brw, params);
 827    gen7_blorp_emit_urb_config(brw);
 828    if (params->wm_prog_data) {
 829       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 830       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 831       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 832       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 833    }
 834    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 835    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 836    if (brw->use_resource_streamer)
 837       gen7_disable_hw_binding_tables(brw);
 838    if (params->wm_prog_data) {
 839       uint32_t wm_surf_offset_renderbuffer;
 840       uint32_t wm_surf_offset_texture = 0;
 841       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 842       intel_miptree_used_for_rendering(params->dst.mt);
 843       wm_surf_offset_renderbuffer =
 844          gen7_blorp_emit_surface_state(brw, &params->dst,
 845                                        I915_GEM_DOMAIN_RENDER,
 846                                        I915_GEM_DOMAIN_RENDER,
 847                                        true /* is_render_target */);
 848       if (params->src.mt) {
 849          wm_surf_offset_texture =
 850             gen7_blorp_emit_surface_state(brw, &params->src,
 851                                           I915_GEM_DOMAIN_SAMPLER, 0,
 852                                           false /* is_render_target */);
 853       }
 854       wm_bind_bo_offset =
 855          gen6_blorp_emit_binding_table(brw,
 856                                        wm_surf_offset_renderbuffer,
 857                                        wm_surf_offset_texture);
 858    }
 859    gen7_blorp_emit_vs_disable(brw);
 860    gen7_blorp_emit_hs_disable(brw);
 861    gen7_blorp_emit_te_disable(brw);
 862    gen7_blorp_emit_ds_disable(brw);
 863    gen7_blorp_emit_gs_disable(brw);
 864    gen7_blorp_emit_streamout_disable(brw);
 865    gen6_blorp_emit_clip_disable(brw);
 866    gen7_blorp_emit_sf_config(brw, params);
 867    gen7_blorp_emit_wm_config(brw, params);
 868    if (params->wm_prog_data) {
 869       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 870       gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
 871    } else {
 872       gen7_blorp_emit_constant_ps_disable(brw);
 873    }
 874
 875    if (params->src.mt) {
 876       const uint32_t sampler_offset =
 877          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 878       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 879    }
 880
 881    gen7_blorp_emit_ps_config(brw, params);
 882    gen7_blorp_emit_cc_viewport(brw);
 883
 884    if (params->depth.mt)
 885       gen7_blorp_emit_depth_stencil_config(brw, params);
 886    else
 887       gen7_blorp_emit_depth_disable(brw);
 888    gen7_blorp_emit_clear_params(brw, params);
 889    gen6_blorp_emit_drawing_rectangle(brw, params);
 890    gen7_blorp_emit_primitive(brw, params);
 891 }