2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen7_blorp.h"
43 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
44 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
46 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
47 * programmed in order for the programming of this state to be
51 gen7_blorp_emit_urb_config(struct brw_context
*brw
,
52 const brw_blorp_params
*params
)
54 unsigned urb_size
= (brw
->is_haswell
&& brw
->gt
== 3) ? 32 : 16;
55 gen7_emit_push_constant_state(brw
,
56 urb_size
/ 2 /* vs_size */,
58 urb_size
/ 2 /* fs_size */);
60 /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
61 * 1.15:0 "VS Number of URB Entries".
63 gen7_emit_urb_state(brw
,
64 32 /* num_vs_entries */,
67 0 /* num_gs_entries */,
73 /* 3DSTATE_BLEND_STATE_POINTERS */
75 gen7_blorp_emit_blend_state_pointer(struct brw_context
*brw
,
76 const brw_blorp_params
*params
,
77 uint32_t cc_blend_state_offset
)
80 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS
<< 16 | (2 - 2));
81 OUT_BATCH(cc_blend_state_offset
| 1);
86 /* 3DSTATE_CC_STATE_POINTERS */
88 gen7_blorp_emit_cc_state_pointer(struct brw_context
*brw
,
89 const brw_blorp_params
*params
,
90 uint32_t cc_state_offset
)
93 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
94 OUT_BATCH(cc_state_offset
| 1);
99 gen7_blorp_emit_cc_viewport(struct brw_context
*brw
,
100 const brw_blorp_params
*params
)
102 struct brw_cc_viewport
*ccv
;
103 uint32_t cc_vp_offset
;
105 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
108 ccv
->min_depth
= 0.0;
109 ccv
->max_depth
= 1.0;
112 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC
<< 16 | (2 - 2));
113 OUT_BATCH(cc_vp_offset
);
118 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
120 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
123 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context
*brw
,
124 const brw_blorp_params
*params
,
125 uint32_t depthstencil_offset
)
128 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
<< 16 | (2 - 2));
129 OUT_BATCH(depthstencil_offset
| 1);
134 /* SURFACE_STATE for renderbuffer or texture surface (see
135 * brw_update_renderbuffer_surface and brw_update_texture_surface)
138 gen7_blorp_emit_surface_state(struct brw_context
*brw
,
139 const brw_blorp_params
*params
,
140 const brw_blorp_surface_info
*surface
,
141 uint32_t read_domains
, uint32_t write_domain
,
142 bool is_render_target
)
144 uint32_t wm_surf_offset
;
145 uint32_t width
= surface
->width
;
146 uint32_t height
= surface
->height
;
147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
148 * color surfaces, width and height are measured in pixels; we don't need
149 * to divide them by 2 as we do for Gen6 (see
150 * gen6_blorp_emit_surface_state).
152 struct intel_mipmap_tree
*mt
= surface
->mt
;
153 uint32_t tile_x
, tile_y
;
154 const uint8_t mocs
= GEN7_MOCS_L3
;
156 uint32_t tiling
= surface
->map_stencil_as_y_tiled
157 ? I915_TILING_Y
: mt
->tiling
;
159 uint32_t *surf
= (uint32_t *)
160 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32, &wm_surf_offset
);
161 memset(surf
, 0, 8 * 4);
163 surf
[0] = BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
164 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
|
165 gen7_surface_tiling_mode(tiling
);
167 if (surface
->mt
->align_h
== 4)
168 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
169 if (surface
->mt
->align_w
== 8)
170 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
172 if (surface
->array_spacing_lod0
)
173 surf
[0] |= GEN7_SURFACE_ARYSPC_LOD0
;
175 surf
[0] |= GEN7_SURFACE_ARYSPC_FULL
;
179 surface
->compute_tile_offsets(&tile_x
, &tile_y
) + mt
->bo
->offset64
;
181 /* Note that the low bits of these fields are missing, so
182 * there's the possibility of getting in trouble.
184 assert(tile_x
% 4 == 0);
185 assert(tile_y
% 2 == 0);
186 surf
[5] = SET_FIELD(tile_x
/ 4, BRW_SURFACE_X_OFFSET
) |
187 SET_FIELD(tile_y
/ 2, BRW_SURFACE_Y_OFFSET
) |
188 SET_FIELD(mocs
, GEN7_SURFACE_MOCS
);
190 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
191 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
193 uint32_t pitch_bytes
= mt
->pitch
;
194 if (surface
->map_stencil_as_y_tiled
)
196 surf
[3] = pitch_bytes
- 1;
198 surf
[4] = gen7_surface_msaa_bits(surface
->num_samples
, surface
->msaa_layout
);
199 if (surface
->mt
->mcs_mt
) {
200 gen7_set_surface_mcs_info(brw
, surf
, wm_surf_offset
, surface
->mt
->mcs_mt
,
204 surf
[7] = surface
->mt
->fast_clear_color_value
;
206 if (brw
->is_haswell
) {
207 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
208 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
209 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
210 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
213 /* Emit relocation to surface contents */
214 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
217 surf
[1] - mt
->bo
->offset64
,
218 read_domains
, write_domain
);
220 gen7_check_surface_setup(surf
, is_render_target
);
222 return wm_surf_offset
;
227 * SAMPLER_STATE. See gen7_update_sampler_state().
230 gen7_blorp_emit_sampler_state(struct brw_context
*brw
,
231 const brw_blorp_params
*params
)
233 uint32_t sampler_offset
;
235 struct gen7_sampler_state
*sampler
= (struct gen7_sampler_state
*)
236 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
237 sizeof(struct gen7_sampler_state
),
238 32, &sampler_offset
);
239 memset(sampler
, 0, sizeof(*sampler
));
241 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
242 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
243 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
245 sampler
->ss3
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
246 sampler
->ss3
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
247 sampler
->ss3
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
249 // sampler->ss0.min_mag_neq = 1;
253 sampler
->ss0
.lod_bias
= 0;
255 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
256 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
258 /* Set BaseMipLevel, MaxLOD, MinLOD:
260 * XXX: I don't think that using firstLevel, lastLevel works,
261 * because we always setup the surface state as if firstLevel ==
262 * level zero. Probably have to subtract firstLevel from each of
265 sampler
->ss0
.base_level
= U_FIXED(0, 1);
267 sampler
->ss1
.max_lod
= U_FIXED(0, 8);
268 sampler
->ss1
.min_lod
= U_FIXED(0, 8);
270 sampler
->ss3
.non_normalized_coord
= 1;
272 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
273 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
274 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
275 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
276 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
277 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
279 return sampler_offset
;
285 * Disable vertex shader.
288 gen7_blorp_emit_vs_disable(struct brw_context
*brw
,
289 const brw_blorp_params
*params
)
292 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (7 - 2));
302 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
314 * Disable the hull shader.
317 gen7_blorp_emit_hs_disable(struct brw_context
*brw
,
318 const brw_blorp_params
*params
)
321 OUT_BATCH(_3DSTATE_CONSTANT_HS
<< 16 | (7 - 2));
331 OUT_BATCH(_3DSTATE_HS
<< 16 | (7 - 2));
344 * Disable the tesselation engine.
347 gen7_blorp_emit_te_disable(struct brw_context
*brw
,
348 const brw_blorp_params
*params
)
351 OUT_BATCH(_3DSTATE_TE
<< 16 | (4 - 2));
361 * Disable the domain shader.
364 gen7_blorp_emit_ds_disable(struct brw_context
*brw
,
365 const brw_blorp_params
*params
)
368 OUT_BATCH(_3DSTATE_CONSTANT_DS
<< 16 | (7 - 2));
378 OUT_BATCH(_3DSTATE_DS
<< 16 | (6 - 2));
389 * Disable the geometry shader.
392 gen7_blorp_emit_gs_disable(struct brw_context
*brw
,
393 const brw_blorp_params
*params
)
396 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (7 - 2));
406 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
407 * Geometry > Geometry Shader > State:
409 * "Note: Because of corruption in IVB:GT2, software needs to flush the
410 * whole fixed function pipeline when the GS enable changes value in
413 * The hardware architects have clarified that in this context "flush the
414 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
417 if (!brw
->is_haswell
&& brw
->gt
== 2 && brw
->gs
.enabled
)
418 gen7_emit_cs_stall_flush(brw
);
421 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
429 brw
->gs
.enabled
= false;
437 gen7_blorp_emit_streamout_disable(struct brw_context
*brw
,
438 const brw_blorp_params
*params
)
441 OUT_BATCH(_3DSTATE_STREAMOUT
<< 16 | (3 - 2));
449 gen7_blorp_emit_sf_config(struct brw_context
*brw
,
450 const brw_blorp_params
*params
)
454 * Disable ViewportTransformEnable (dw1.1)
456 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
457 * Primitives Overview":
458 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
459 * use of screen- space coordinates).
461 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
462 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
464 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
465 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
466 * SOLID: Any triangle or rectangle object found to be front-facing
467 * is rendered as a solid object. This setting is required when
468 * (rendering rectangle (RECTLIST) objects.
472 OUT_BATCH(_3DSTATE_SF
<< 16 | (7 - 2));
473 OUT_BATCH(params
->depth_format
<<
474 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT
);
475 OUT_BATCH(params
->dst
.num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
486 OUT_BATCH(_3DSTATE_SBE
<< 16 | (14 - 2));
487 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT
| /* only position */
488 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT
|
489 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT
);
490 for (int i
= 0; i
< 12; ++i
)
498 * Disable thread dispatch (dw5.19) and enable the HiZ op.
501 gen7_blorp_emit_wm_config(struct brw_context
*brw
,
502 const brw_blorp_params
*params
,
503 brw_blorp_prog_data
*prog_data
)
505 uint32_t dw1
= 0, dw2
= 0;
507 switch (params
->hiz_op
) {
508 case GEN6_HIZ_OP_DEPTH_CLEAR
:
509 dw1
|= GEN7_WM_DEPTH_CLEAR
;
511 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
512 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
514 case GEN6_HIZ_OP_HIZ_RESOLVE
:
515 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
517 case GEN6_HIZ_OP_NONE
:
520 unreachable("not reached");
522 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
523 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
524 dw1
|= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
525 if (params
->use_wm_prog
) {
526 dw1
|= GEN7_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
527 dw1
|= GEN7_WM_DISPATCH_ENABLE
; /* We are rendering */
530 if (params
->dst
.num_samples
> 1) {
531 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
532 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
533 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
535 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
537 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
538 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
542 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
552 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
553 * that, thread dispatch info must still be specified.
554 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
555 * valid range for this field is [0x3, 0x2f].
556 * - A dispatch mode must be given; that is, at least one of the
557 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
558 * discovered through simulator error messages.
561 gen7_blorp_emit_ps_config(struct brw_context
*brw
,
562 const brw_blorp_params
*params
,
563 uint32_t prog_offset
,
564 brw_blorp_prog_data
*prog_data
)
566 uint32_t dw2
, dw4
, dw5
;
567 const int max_threads_shift
= brw
->is_haswell
?
568 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
571 dw4
|= (brw
->max_wm_threads
- 1) << max_threads_shift
;
573 /* If there's a WM program, we need to do 16-pixel dispatch since that's
574 * what the program is compiled for. If there isn't, then it shouldn't
575 * matter because no program is actually being run. However, the hardware
576 * gets angry if we don't enable at least one dispatch mode, so just enable
577 * 16-pixel dispatch unconditionally.
579 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
582 dw4
|= SET_FIELD(1, HSW_PS_SAMPLE_MASK
); /* 1 sample for now */
583 if (params
->use_wm_prog
) {
584 dw2
|= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
585 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
586 dw5
|= prog_data
->first_curbe_grf
<< GEN7_PS_DISPATCH_START_GRF_SHIFT_0
;
589 switch (params
->fast_clear_op
) {
590 case GEN7_FAST_CLEAR_OP_FAST_CLEAR
:
591 dw4
|= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE
;
593 case GEN7_FAST_CLEAR_OP_RESOLVE
:
594 dw4
|= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE
;
601 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
602 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
614 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context
*brw
,
615 const brw_blorp_params
*params
,
616 uint32_t wm_bind_bo_offset
)
619 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS
<< 16 | (2 - 2));
620 OUT_BATCH(wm_bind_bo_offset
);
626 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context
*brw
,
627 const brw_blorp_params
*params
,
628 uint32_t sampler_offset
)
631 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
632 OUT_BATCH(sampler_offset
);
638 gen7_blorp_emit_constant_ps(struct brw_context
*brw
,
639 const brw_blorp_params
*params
,
640 uint32_t wm_push_const_offset
)
642 const uint8_t mocs
= GEN7_MOCS_L3
;
644 /* Make sure the push constants fill an exact integer number of
647 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
649 /* There must be at least one register worth of push constant data. */
650 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
652 /* Enable push constant buffer 0. */
654 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
656 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS
);
658 OUT_BATCH(wm_push_const_offset
| mocs
);
666 gen7_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
667 const brw_blorp_params
*params
)
670 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (7 - 2));
681 gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
682 const brw_blorp_params
*params
)
684 const uint8_t mocs
= GEN7_MOCS_L3
;
685 uint32_t surfwidth
, surfheight
;
687 unsigned int depth
= MAX2(params
->depth
.mt
->logical_depth0
, 1);
688 unsigned int min_array_element
;
689 GLenum gl_target
= params
->depth
.mt
->target
;
693 case GL_TEXTURE_CUBE_MAP_ARRAY
:
694 case GL_TEXTURE_CUBE_MAP
:
695 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
696 * situation, but experiments show that gl_Layer doesn't work when we do
697 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
700 surftype
= BRW_SURFACE_2D
;
704 surftype
= translate_tex_target(gl_target
);
708 min_array_element
= params
->depth
.layer
;
709 if (params
->depth
.mt
->num_samples
> 1) {
710 /* Convert physical layer to logical layer. */
711 min_array_element
/= params
->depth
.mt
->num_samples
;
714 lod
= params
->depth
.level
- params
->depth
.mt
->first_level
;
716 if (params
->hiz_op
!= GEN6_HIZ_OP_NONE
&& lod
== 0) {
717 /* HIZ ops for lod 0 may set the width & height a little
718 * larger to allow the fast depth clear to fit the hardware
719 * alignment requirements. (8x4)
721 surfwidth
= params
->depth
.width
;
722 surfheight
= params
->depth
.height
;
724 surfwidth
= params
->depth
.mt
->logical_width0
;
725 surfheight
= params
->depth
.mt
->logical_height0
;
728 /* 3DSTATE_DEPTH_BUFFER */
730 intel_emit_depth_stall_flushes(brw
);
733 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
734 OUT_BATCH((params
->depth
.mt
->pitch
- 1) |
735 params
->depth_format
<< 18 |
736 1 << 22 | /* hiz enable */
737 1 << 28 | /* depth write */
739 OUT_RELOC(params
->depth
.mt
->bo
,
740 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
742 OUT_BATCH((surfwidth
- 1) << 4 |
743 (surfheight
- 1) << 18 |
745 OUT_BATCH(((depth
- 1) << 21) |
746 (min_array_element
<< 10) |
749 OUT_BATCH((depth
- 1) << 21);
753 /* 3DSTATE_HIER_DEPTH_BUFFER */
755 struct intel_mipmap_tree
*hiz_mt
= params
->depth
.mt
->hiz_mt
;
758 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
759 OUT_BATCH((mocs
<< 25) |
760 (hiz_mt
->pitch
- 1));
761 OUT_RELOC(hiz_mt
->bo
,
762 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
767 /* 3DSTATE_STENCIL_BUFFER */
770 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
779 gen7_blorp_emit_depth_disable(struct brw_context
*brw
,
780 const brw_blorp_params
*params
)
782 intel_emit_depth_stall_flushes(brw
);
785 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
786 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT
<< 18 | (BRW_SURFACE_NULL
<< 29));
795 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
801 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
808 /* 3DSTATE_CLEAR_PARAMS
810 * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
811 * 3DSTATE_CLEAR_PARAMS:
812 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along
813 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
814 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
817 gen7_blorp_emit_clear_params(struct brw_context
*brw
,
818 const brw_blorp_params
*params
)
821 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
822 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
823 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID
);
830 gen7_blorp_emit_primitive(struct brw_context
*brw
,
831 const brw_blorp_params
*params
)
834 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
835 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
|
837 OUT_BATCH(3); /* vertex count per instance */
839 OUT_BATCH(1); /* instance count */
847 * \copydoc gen6_blorp_exec()
850 gen7_blorp_exec(struct brw_context
*brw
,
851 const brw_blorp_params
*params
)
856 brw_blorp_prog_data
*prog_data
= NULL
;
857 uint32_t cc_blend_state_offset
= 0;
858 uint32_t cc_state_offset
= 0;
859 uint32_t depthstencil_offset
;
860 uint32_t wm_push_const_offset
= 0;
861 uint32_t wm_bind_bo_offset
= 0;
862 uint32_t sampler_offset
= 0;
864 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
865 gen6_emit_3dstate_multisample(brw
, params
->dst
.num_samples
);
866 gen6_emit_3dstate_sample_mask(brw
,
867 params
->dst
.num_samples
> 1 ?
868 (1 << params
->dst
.num_samples
) - 1 : 1);
869 gen6_blorp_emit_state_base_address(brw
, params
);
870 gen6_blorp_emit_vertices(brw
, params
);
871 gen7_blorp_emit_urb_config(brw
, params
);
872 if (params
->use_wm_prog
) {
873 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
874 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
875 gen7_blorp_emit_blend_state_pointer(brw
, params
, cc_blend_state_offset
);
876 gen7_blorp_emit_cc_state_pointer(brw
, params
, cc_state_offset
);
878 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
879 gen7_blorp_emit_depth_stencil_state_pointers(brw
, params
,
880 depthstencil_offset
);
881 if (params
->use_wm_prog
) {
882 uint32_t wm_surf_offset_renderbuffer
;
883 uint32_t wm_surf_offset_texture
= 0;
884 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
885 intel_miptree_used_for_rendering(params
->dst
.mt
);
886 wm_surf_offset_renderbuffer
=
887 gen7_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
888 I915_GEM_DOMAIN_RENDER
,
889 I915_GEM_DOMAIN_RENDER
,
890 true /* is_render_target */);
891 if (params
->src
.mt
) {
892 wm_surf_offset_texture
=
893 gen7_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
894 I915_GEM_DOMAIN_SAMPLER
, 0,
895 false /* is_render_target */);
898 gen6_blorp_emit_binding_table(brw
, params
,
899 wm_surf_offset_renderbuffer
,
900 wm_surf_offset_texture
);
901 sampler_offset
= gen7_blorp_emit_sampler_state(brw
, params
);
903 gen7_blorp_emit_vs_disable(brw
, params
);
904 gen7_blorp_emit_hs_disable(brw
, params
);
905 gen7_blorp_emit_te_disable(brw
, params
);
906 gen7_blorp_emit_ds_disable(brw
, params
);
907 gen7_blorp_emit_gs_disable(brw
, params
);
908 gen7_blorp_emit_streamout_disable(brw
, params
);
909 gen6_blorp_emit_clip_disable(brw
, params
);
910 gen7_blorp_emit_sf_config(brw
, params
);
911 gen7_blorp_emit_wm_config(brw
, params
, prog_data
);
912 if (params
->use_wm_prog
) {
913 gen7_blorp_emit_binding_table_pointers_ps(brw
, params
,
915 gen7_blorp_emit_sampler_state_pointers_ps(brw
, params
, sampler_offset
);
916 gen7_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
918 gen7_blorp_emit_constant_ps_disable(brw
, params
);
920 gen7_blorp_emit_ps_config(brw
, params
, prog_offset
, prog_data
);
921 gen7_blorp_emit_cc_viewport(brw
, params
);
923 if (params
->depth
.mt
)
924 gen7_blorp_emit_depth_stencil_config(brw
, params
);
926 gen7_blorp_emit_depth_disable(brw
, params
);
927 gen7_blorp_emit_clear_params(brw
, params
);
928 gen6_blorp_emit_drawing_rectangle(brw
, params
);
929 gen7_blorp_emit_primitive(brw
, params
);