src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  44  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  45  *
  46  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  47  *     programmed in order for the programming of this state to be
  48  *     valid.
  49  */
  50 static void
  51 gen7_blorp_emit_urb_config(struct brw_context *brw,
  52                            const brw_blorp_params *params)
  53 {
  54    unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
  55    gen7_emit_push_constant_state(brw,
  56                                  urb_size / 2 /* vs_size */,
  57                                  0 /* gs_size */,
  58                                  urb_size / 2 /* fs_size */);
  59
  60    /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
  61     * 1.15:0 "VS Number of URB Entries".
  62     */
  63    gen7_emit_urb_state(brw,
  64                        32 /* num_vs_entries */,
  65                        2 /* vs_size */,
  66                        2 /* vs_start */,
  67                        0 /* num_gs_entries */,
  68                        1 /* gs_size */,
  69                        2 /* gs_start */);
  70 }
  71
  72
  73 /* 3DSTATE_BLEND_STATE_POINTERS */
  74 static void
  75 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  76                                     const brw_blorp_params *params,
  77                                     uint32_t cc_blend_state_offset)
  78 {
  79    BEGIN_BATCH(2);
  80    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  81    OUT_BATCH(cc_blend_state_offset | 1);
  82    ADVANCE_BATCH();
  83 }
  84
  85
  86 /* 3DSTATE_CC_STATE_POINTERS */
  87 static void
  88 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  89                                  const brw_blorp_params *params,
  90                                  uint32_t cc_state_offset)
  91 {
  92    BEGIN_BATCH(2);
  93    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  94    OUT_BATCH(cc_state_offset | 1);
  95    ADVANCE_BATCH();
  96 }
  97
  98 static void
  99 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
 100                             const brw_blorp_params *params)
 101 {
 102    struct brw_cc_viewport *ccv;
 103    uint32_t cc_vp_offset;
 104
 105    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 106                                                    sizeof(*ccv), 32,
 107                                                    &cc_vp_offset);
 108    ccv->min_depth = 0.0;
 109    ccv->max_depth = 1.0;
 110
 111    BEGIN_BATCH(2);
 112    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 113    OUT_BATCH(cc_vp_offset);
 114    ADVANCE_BATCH();
 115 }
 116
 117
 118 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 119  *
 120  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 121  */
 122 static void
 123 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 124                                              const brw_blorp_params *params,
 125                                              uint32_t depthstencil_offset)
 126 {
 127    BEGIN_BATCH(2);
 128    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 129    OUT_BATCH(depthstencil_offset | 1);
 130    ADVANCE_BATCH();
 131 }
 132
 133
 134 /* SURFACE_STATE for renderbuffer or texture surface (see
 135  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 136  */
 137 static uint32_t
 138 gen7_blorp_emit_surface_state(struct brw_context *brw,
 139                               const brw_blorp_params *params,
 140                               const brw_blorp_surface_info *surface,
 141                               uint32_t read_domains, uint32_t write_domain,
 142                               bool is_render_target)
 143 {
 144    uint32_t wm_surf_offset;
 145    uint32_t width = surface->width;
 146    uint32_t height = surface->height;
 147    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 148     * color surfaces, width and height are measured in pixels; we don't need
 149     * to divide them by 2 as we do for Gen6 (see
 150     * gen6_blorp_emit_surface_state).
 151     */
 152    struct intel_mipmap_tree *mt = surface->mt;
 153    uint32_t tile_x, tile_y;
 154    const uint8_t mocs = GEN7_MOCS_L3;
 155
 156    uint32_t tiling = surface->map_stencil_as_y_tiled
 157       ? I915_TILING_Y : mt->tiling;
 158
 159    uint32_t *surf = (uint32_t *)
 160       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 161    memset(surf, 0, 8 * 4);
 162
 163    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 164              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 165              gen7_surface_tiling_mode(tiling);
 166
 167    if (surface->mt->align_h == 4)
 168       surf[0] |= GEN7_SURFACE_VALIGN_4;
 169    if (surface->mt->align_w == 8)
 170       surf[0] |= GEN7_SURFACE_HALIGN_8;
 171
 172    if (surface->array_spacing_lod0)
 173       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 174    else
 175       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 176
 177    /* reloc */
 178    surf[1] =
 179       surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
 180
 181    /* Note that the low bits of these fields are missing, so
 182     * there's the possibility of getting in trouble.
 183     */
 184    assert(tile_x % 4 == 0);
 185    assert(tile_y % 2 == 0);
 186    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 187              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 188              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 189
 190    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 191              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 192
 193    uint32_t pitch_bytes = mt->pitch;
 194    if (surface->map_stencil_as_y_tiled)
 195       pitch_bytes *= 2;
 196    surf[3] = pitch_bytes - 1;
 197
 198    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 199    if (surface->mt->mcs_mt) {
 200       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 201                                 is_render_target);
 202    }
 203
 204    surf[7] = surface->mt->fast_clear_color_value;
 205
 206    if (brw->is_haswell) {
 207       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 208                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 209                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 210                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 211    }
 212
 213    /* Emit relocation to surface contents */
 214    drm_intel_bo_emit_reloc(brw->batch.bo,
 215                            wm_surf_offset + 4,
 216                            mt->bo,
 217                            surf[1] - mt->bo->offset64,
 218                            read_domains, write_domain);
 219
 220    gen7_check_surface_setup(surf, is_render_target);
 221
 222    return wm_surf_offset;
 223 }
 224
 225
 226 /* 3DSTATE_VS
 227  *
 228  * Disable vertex shader.
 229  */
 230 static void
 231 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 232                            const brw_blorp_params *params)
 233 {
 234    BEGIN_BATCH(7);
 235    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 236    OUT_BATCH(0);
 237    OUT_BATCH(0);
 238    OUT_BATCH(0);
 239    OUT_BATCH(0);
 240    OUT_BATCH(0);
 241    OUT_BATCH(0);
 242    ADVANCE_BATCH();
 243
 244    BEGIN_BATCH(6);
 245    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 246    OUT_BATCH(0);
 247    OUT_BATCH(0);
 248    OUT_BATCH(0);
 249    OUT_BATCH(0);
 250    OUT_BATCH(0);
 251    ADVANCE_BATCH();
 252 }
 253
 254
 255 /* 3DSTATE_HS
 256  *
 257  * Disable the hull shader.
 258  */
 259 static void
 260 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 261                            const brw_blorp_params *params)
 262 {
 263    BEGIN_BATCH(7);
 264    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 265    OUT_BATCH(0);
 266    OUT_BATCH(0);
 267    OUT_BATCH(0);
 268    OUT_BATCH(0);
 269    OUT_BATCH(0);
 270    OUT_BATCH(0);
 271    ADVANCE_BATCH();
 272
 273    BEGIN_BATCH(7);
 274    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 275    OUT_BATCH(0);
 276    OUT_BATCH(0);
 277    OUT_BATCH(0);
 278    OUT_BATCH(0);
 279    OUT_BATCH(0);
 280    OUT_BATCH(0);
 281    ADVANCE_BATCH();
 282 }
 283
 284
 285 /* 3DSTATE_TE
 286  *
 287  * Disable the tesselation engine.
 288  */
 289 static void
 290 gen7_blorp_emit_te_disable(struct brw_context *brw,
 291                            const brw_blorp_params *params)
 292 {
 293    BEGIN_BATCH(4);
 294    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    ADVANCE_BATCH();
 299 }
 300
 301
 302 /* 3DSTATE_DS
 303  *
 304  * Disable the domain shader.
 305  */
 306 static void
 307 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 308                            const brw_blorp_params *params)
 309 {
 310    BEGIN_BATCH(7);
 311    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 312    OUT_BATCH(0);
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    ADVANCE_BATCH();
 319
 320    BEGIN_BATCH(6);
 321    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    ADVANCE_BATCH();
 328 }
 329
 330 /* 3DSTATE_GS
 331  *
 332  * Disable the geometry shader.
 333  */
 334 static void
 335 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 336                            const brw_blorp_params *params)
 337 {
 338    BEGIN_BATCH(7);
 339    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 340    OUT_BATCH(0);
 341    OUT_BATCH(0);
 342    OUT_BATCH(0);
 343    OUT_BATCH(0);
 344    OUT_BATCH(0);
 345    OUT_BATCH(0);
 346    ADVANCE_BATCH();
 347
 348    /**
 349     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 350     * Geometry > Geometry Shader > State:
 351     *
 352     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 353     *     whole fixed function pipeline when the GS enable changes value in
 354     *     the 3DSTATE_GS."
 355     *
 356     * The hardware architects have clarified that in this context "flush the
 357     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 358     * Stall" bit set.
 359     */
 360    if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 361       gen7_emit_cs_stall_flush(brw);
 362
 363    BEGIN_BATCH(7);
 364    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 365    OUT_BATCH(0);
 366    OUT_BATCH(0);
 367    OUT_BATCH(0);
 368    OUT_BATCH(0);
 369    OUT_BATCH(0);
 370    OUT_BATCH(0);
 371    ADVANCE_BATCH();
 372    brw->gs.enabled = false;
 373 }
 374
 375 /* 3DSTATE_STREAMOUT
 376  *
 377  * Disable streamout.
 378  */
 379 static void
 380 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 381                                   const brw_blorp_params *params)
 382 {
 383    BEGIN_BATCH(3);
 384    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 385    OUT_BATCH(0);
 386    OUT_BATCH(0);
 387    ADVANCE_BATCH();
 388 }
 389
 390
 391 static void
 392 gen7_blorp_emit_sf_config(struct brw_context *brw,
 393                           const brw_blorp_params *params)
 394 {
 395    /* 3DSTATE_SF
 396     *
 397     * Disable ViewportTransformEnable (dw1.1)
 398     *
 399     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 400     * Primitives Overview":
 401     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 402     *     use of screen- space coordinates).
 403     *
 404     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 405     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 406     *
 407     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 408     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 409     *     SOLID: Any triangle or rectangle object found to be front-facing
 410     *     is rendered as a solid object. This setting is required when
 411     *     (rendering rectangle (RECTLIST) objects.
 412     */
 413    {
 414       BEGIN_BATCH(7);
 415       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 416       OUT_BATCH(params->depth_format <<
 417                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 418       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 419       OUT_BATCH(0);
 420       OUT_BATCH(0);
 421       OUT_BATCH(0);
 422       OUT_BATCH(0);
 423       ADVANCE_BATCH();
 424    }
 425
 426    /* 3DSTATE_SBE */
 427    {
 428       BEGIN_BATCH(14);
 429       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 430       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 431                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 432                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 433       for (int i = 0; i < 12; ++i)
 434          OUT_BATCH(0);
 435       ADVANCE_BATCH();
 436    }
 437 }
 438
 439
 440 /**
 441  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 442  */
 443 static void
 444 gen7_blorp_emit_wm_config(struct brw_context *brw,
 445                           const brw_blorp_params *params,
 446                           brw_blorp_prog_data *prog_data)
 447 {
 448    uint32_t dw1 = 0, dw2 = 0;
 449
 450    switch (params->hiz_op) {
 451    case GEN6_HIZ_OP_DEPTH_CLEAR:
 452       dw1 |= GEN7_WM_DEPTH_CLEAR;
 453       break;
 454    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 455       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 456       break;
 457    case GEN6_HIZ_OP_HIZ_RESOLVE:
 458       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 459       break;
 460    case GEN6_HIZ_OP_NONE:
 461       break;
 462    default:
 463       unreachable("not reached");
 464    }
 465    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 466    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 467    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 468    if (params->use_wm_prog) {
 469       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 470       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 471    }
 472
 473       if (params->dst.num_samples > 1) {
 474          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 475          if (prog_data && prog_data->persample_msaa_dispatch)
 476             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 477          else
 478             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 479       } else {
 480          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 481          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 482       }
 483
 484    BEGIN_BATCH(3);
 485    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 486    OUT_BATCH(dw1);
 487    OUT_BATCH(dw2);
 488    ADVANCE_BATCH();
 489 }
 490
 491
 492 /**
 493  * 3DSTATE_PS
 494  *
 495  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 496  * that, thread dispatch info must still be specified.
 497  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 498  *       valid range for this field is [0x3, 0x2f].
 499  *     - A dispatch mode must be given; that is, at least one of the
 500  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 501  *       discovered through simulator error messages.
 502  */
 503 static void
 504 gen7_blorp_emit_ps_config(struct brw_context *brw,
 505                           const brw_blorp_params *params,
 506                           uint32_t prog_offset,
 507                           brw_blorp_prog_data *prog_data)
 508 {
 509    uint32_t dw2, dw4, dw5;
 510    const int max_threads_shift = brw->is_haswell ?
 511       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 512
 513    dw2 = dw4 = dw5 = 0;
 514    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 515
 516    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 517     * what the program is compiled for.  If there isn't, then it shouldn't
 518     * matter because no program is actually being run.  However, the hardware
 519     * gets angry if we don't enable at least one dispatch mode, so just enable
 520     * 16-pixel dispatch unconditionally.
 521     */
 522    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 523
 524    if (brw->is_haswell)
 525       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 526    if (params->use_wm_prog) {
 527       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 528       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 529       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 530    }
 531
 532    switch (params->fast_clear_op) {
 533    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 534       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 535       break;
 536    case GEN7_FAST_CLEAR_OP_RESOLVE:
 537       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 538       break;
 539    default:
 540       break;
 541    }
 542
 543    BEGIN_BATCH(8);
 544    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 545    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 546    OUT_BATCH(dw2);
 547    OUT_BATCH(0);
 548    OUT_BATCH(dw4);
 549    OUT_BATCH(dw5);
 550    OUT_BATCH(0);
 551    OUT_BATCH(0);
 552    ADVANCE_BATCH();
 553 }
 554
 555
 556 static void
 557 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 558                                           const brw_blorp_params *params,
 559                                           uint32_t wm_bind_bo_offset)
 560 {
 561    BEGIN_BATCH(2);
 562    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 563    OUT_BATCH(wm_bind_bo_offset);
 564    ADVANCE_BATCH();
 565 }
 566
 567
 568 static void
 569 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 570                                           const brw_blorp_params *params,
 571                                           uint32_t sampler_offset)
 572 {
 573    BEGIN_BATCH(2);
 574    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 575    OUT_BATCH(sampler_offset);
 576    ADVANCE_BATCH();
 577 }
 578
 579
 580 static void
 581 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 582                             const brw_blorp_params *params,
 583                             uint32_t wm_push_const_offset)
 584 {
 585    const uint8_t mocs = GEN7_MOCS_L3;
 586
 587    /* Make sure the push constants fill an exact integer number of
 588     * registers.
 589     */
 590    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 591
 592    /* There must be at least one register worth of push constant data. */
 593    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 594
 595    /* Enable push constant buffer 0. */
 596    BEGIN_BATCH(7);
 597    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 598              (7 - 2));
 599    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 600    OUT_BATCH(0);
 601    OUT_BATCH(wm_push_const_offset | mocs);
 602    OUT_BATCH(0);
 603    OUT_BATCH(0);
 604    OUT_BATCH(0);
 605    ADVANCE_BATCH();
 606 }
 607
 608 static void
 609 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 610                                     const brw_blorp_params *params)
 611 {
 612    BEGIN_BATCH(7);
 613    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 614    OUT_BATCH(0);
 615    OUT_BATCH(0);
 616    OUT_BATCH(0);
 617    OUT_BATCH(0);
 618    OUT_BATCH(0);
 619    OUT_BATCH(0);
 620    ADVANCE_BATCH();
 621 }
 622
 623 static void
 624 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 625                                      const brw_blorp_params *params)
 626 {
 627    const uint8_t mocs = GEN7_MOCS_L3;
 628    uint32_t surfwidth, surfheight;
 629    uint32_t surftype;
 630    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 631    unsigned int min_array_element;
 632    GLenum gl_target = params->depth.mt->target;
 633    unsigned int lod;
 634
 635    switch (gl_target) {
 636    case GL_TEXTURE_CUBE_MAP_ARRAY:
 637    case GL_TEXTURE_CUBE_MAP:
 638       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 639        * situation, but experiments show that gl_Layer doesn't work when we do
 640        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 641        * equivalent.
 642        */
 643       surftype = BRW_SURFACE_2D;
 644       depth *= 6;
 645       break;
 646    default:
 647       surftype = translate_tex_target(gl_target);
 648       break;
 649    }
 650
 651    min_array_element = params->depth.layer;
 652    if (params->depth.mt->num_samples > 1) {
 653       /* Convert physical layer to logical layer. */
 654       min_array_element /= params->depth.mt->num_samples;
 655    }
 656
 657    lod = params->depth.level - params->depth.mt->first_level;
 658
 659    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 660       /* HIZ ops for lod 0 may set the width & height a little
 661        * larger to allow the fast depth clear to fit the hardware
 662        * alignment requirements. (8x4)
 663        */
 664       surfwidth = params->depth.width;
 665       surfheight = params->depth.height;
 666    } else {
 667       surfwidth = params->depth.mt->logical_width0;
 668       surfheight = params->depth.mt->logical_height0;
 669    }
 670
 671    /* 3DSTATE_DEPTH_BUFFER */
 672    {
 673       intel_emit_depth_stall_flushes(brw);
 674
 675       BEGIN_BATCH(7);
 676       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 677       OUT_BATCH((params->depth.mt->pitch - 1) |
 678                 params->depth_format << 18 |
 679                 1 << 22 | /* hiz enable */
 680                 1 << 28 | /* depth write */
 681                 surftype << 29);
 682       OUT_RELOC(params->depth.mt->bo,
 683                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 684                 0);
 685       OUT_BATCH((surfwidth - 1) << 4 |
 686                 (surfheight - 1) << 18 |
 687                 lod);
 688       OUT_BATCH(((depth - 1) << 21) |
 689                 (min_array_element << 10) |
 690                 mocs);
 691       OUT_BATCH(0);
 692       OUT_BATCH((depth - 1) << 21);
 693       ADVANCE_BATCH();
 694    }
 695
 696    /* 3DSTATE_HIER_DEPTH_BUFFER */
 697    {
 698       struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
 699
 700       BEGIN_BATCH(3);
 701       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 702       OUT_BATCH((mocs << 25) |
 703                 (hiz_mt->pitch - 1));
 704       OUT_RELOC(hiz_mt->bo,
 705                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 706                 0);
 707       ADVANCE_BATCH();
 708    }
 709
 710    /* 3DSTATE_STENCIL_BUFFER */
 711    {
 712       BEGIN_BATCH(3);
 713       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 714       OUT_BATCH(0);
 715       OUT_BATCH(0);
 716       ADVANCE_BATCH();
 717    }
 718 }
 719
 720
 721 static void
 722 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 723                               const brw_blorp_params *params)
 724 {
 725    intel_emit_depth_stall_flushes(brw);
 726
 727    BEGIN_BATCH(7);
 728    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 729    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 730    OUT_BATCH(0);
 731    OUT_BATCH(0);
 732    OUT_BATCH(0);
 733    OUT_BATCH(0);
 734    OUT_BATCH(0);
 735    ADVANCE_BATCH();
 736
 737    BEGIN_BATCH(3);
 738    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 739    OUT_BATCH(0);
 740    OUT_BATCH(0);
 741    ADVANCE_BATCH();
 742
 743    BEGIN_BATCH(3);
 744    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 745    OUT_BATCH(0);
 746    OUT_BATCH(0);
 747    ADVANCE_BATCH();
 748 }
 749
 750
 751 /* 3DSTATE_CLEAR_PARAMS
 752  *
 753  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 754  * 3DSTATE_CLEAR_PARAMS:
 755  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 756  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 757  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 758  */
 759 static void
 760 gen7_blorp_emit_clear_params(struct brw_context *brw,
 761                              const brw_blorp_params *params)
 762 {
 763    BEGIN_BATCH(3);
 764    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 765    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 766    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 767    ADVANCE_BATCH();
 768 }
 769
 770
 771 /* 3DPRIMITIVE */
 772 static void
 773 gen7_blorp_emit_primitive(struct brw_context *brw,
 774                           const brw_blorp_params *params)
 775 {
 776    BEGIN_BATCH(7);
 777    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 778    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 779              _3DPRIM_RECTLIST);
 780    OUT_BATCH(3); /* vertex count per instance */
 781    OUT_BATCH(0);
 782    OUT_BATCH(1); /* instance count */
 783    OUT_BATCH(0);
 784    OUT_BATCH(0);
 785    ADVANCE_BATCH();
 786 }
 787
 788
 789 /**
 790  * \copydoc gen6_blorp_exec()
 791  */
 792 void
 793 gen7_blorp_exec(struct brw_context *brw,
 794                 const brw_blorp_params *params)
 795 {
 796    if (brw->gen >= 8)
 797       return;
 798
 799    brw_blorp_prog_data *prog_data = NULL;
 800    uint32_t cc_blend_state_offset = 0;
 801    uint32_t cc_state_offset = 0;
 802    uint32_t depthstencil_offset;
 803    uint32_t wm_push_const_offset = 0;
 804    uint32_t wm_bind_bo_offset = 0;
 805    uint32_t sampler_offset = 0;
 806
 807    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 808    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 809    gen6_emit_3dstate_sample_mask(brw,
 810                                  params->dst.num_samples > 1 ?
 811                                  (1 << params->dst.num_samples) - 1 : 1);
 812    gen6_blorp_emit_state_base_address(brw, params);
 813    gen6_blorp_emit_vertices(brw, params);
 814    gen7_blorp_emit_urb_config(brw, params);
 815    if (params->use_wm_prog) {
 816       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 817       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 818       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 819       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 820    }
 821    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 822    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 823                                                 depthstencil_offset);
 824    if (params->use_wm_prog) {
 825       uint32_t wm_surf_offset_renderbuffer;
 826       uint32_t wm_surf_offset_texture = 0;
 827       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 828       intel_miptree_used_for_rendering(params->dst.mt);
 829       wm_surf_offset_renderbuffer =
 830          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 831                                        I915_GEM_DOMAIN_RENDER,
 832                                        I915_GEM_DOMAIN_RENDER,
 833                                        true /* is_render_target */);
 834       if (params->src.mt) {
 835          wm_surf_offset_texture =
 836             gen7_blorp_emit_surface_state(brw, params, &params->src,
 837                                           I915_GEM_DOMAIN_SAMPLER, 0,
 838                                           false /* is_render_target */);
 839       }
 840       wm_bind_bo_offset =
 841          gen6_blorp_emit_binding_table(brw, params,
 842                                        wm_surf_offset_renderbuffer,
 843                                        wm_surf_offset_texture);
 844       sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
 845    }
 846    gen7_blorp_emit_vs_disable(brw, params);
 847    gen7_blorp_emit_hs_disable(brw, params);
 848    gen7_blorp_emit_te_disable(brw, params);
 849    gen7_blorp_emit_ds_disable(brw, params);
 850    gen7_blorp_emit_gs_disable(brw, params);
 851    gen7_blorp_emit_streamout_disable(brw, params);
 852    gen6_blorp_emit_clip_disable(brw, params);
 853    gen7_blorp_emit_sf_config(brw, params);
 854    gen7_blorp_emit_wm_config(brw, params, prog_data);
 855    if (params->use_wm_prog) {
 856       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 857                                                 wm_bind_bo_offset);
 858       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 859       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 860    } else {
 861       gen7_blorp_emit_constant_ps_disable(brw, params);
 862    }
 863    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 864    gen7_blorp_emit_cc_viewport(brw, params);
 865
 866    if (params->depth.mt)
 867       gen7_blorp_emit_depth_stencil_config(brw, params);
 868    else
 869       gen7_blorp_emit_depth_disable(brw, params);
 870    gen7_blorp_emit_clear_params(brw, params);
 871    gen6_blorp_emit_drawing_rectangle(brw, params);
 872    gen7_blorp_emit_primitive(brw, params);
 873 }