src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "brw_blorp.h"
  33
  34
  35 /* 3DSTATE_URB_VS
  36  * 3DSTATE_URB_HS
  37  * 3DSTATE_URB_DS
  38  * 3DSTATE_URB_GS
  39  *
  40  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  41  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  42  *
  43  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  44  *     programmed in order for the programming of this state to be
  45  *     valid.
  46  */
  47 static void
  48 gen7_blorp_emit_urb_config(struct brw_context *brw)
  49 {
  50    unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
  51    gen7_emit_push_constant_state(brw,
  52                                  urb_size / 2 /* vs_size */,
  53                                  0 /* hs_size */,
  54                                  0 /* ds_size */,
  55                                  0 /* gs_size */,
  56                                  urb_size / 2 /* fs_size */);
  57
  58    /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
  59     * 1.15:0 "VS Number of URB Entries".
  60     */
  61    gen7_emit_urb_state(brw,
  62                        32 /* num_vs_entries */,
  63                        2 /* vs_size */,
  64                        2 /* vs_start */,
  65                        0 /* num_hs_entries */,
  66                        1 /* hs_size */,
  67                        2 /* hs_start */,
  68                        0 /* num_ds_entries */,
  69                        1 /* ds_size */,
  70                        2 /* ds_start */,
  71                        0 /* num_gs_entries */,
  72                        1 /* gs_size */,
  73                        2 /* gs_start */);
  74 }
  75
  76
  77 /* 3DSTATE_BLEND_STATE_POINTERS */
  78 static void
  79 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  80                                     uint32_t cc_blend_state_offset)
  81 {
  82    BEGIN_BATCH(2);
  83    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  84    OUT_BATCH(cc_blend_state_offset | 1);
  85    ADVANCE_BATCH();
  86 }
  87
  88
  89 /* 3DSTATE_CC_STATE_POINTERS */
  90 static void
  91 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  92                                  uint32_t cc_state_offset)
  93 {
  94    BEGIN_BATCH(2);
  95    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  96    OUT_BATCH(cc_state_offset | 1);
  97    ADVANCE_BATCH();
  98 }
  99
 100 static void
 101 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 102 {
 103    struct brw_cc_viewport *ccv;
 104    uint32_t cc_vp_offset;
 105
 106    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 107                                                    sizeof(*ccv), 32,
 108                                                    &cc_vp_offset);
 109    ccv->min_depth = 0.0;
 110    ccv->max_depth = 1.0;
 111
 112    BEGIN_BATCH(2);
 113    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 114    OUT_BATCH(cc_vp_offset);
 115    ADVANCE_BATCH();
 116 }
 117
 118
 119 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 120  *
 121  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 122  */
 123 static void
 124 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 125                                              uint32_t depthstencil_offset)
 126 {
 127    BEGIN_BATCH(2);
 128    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 129    OUT_BATCH(depthstencil_offset | 1);
 130    ADVANCE_BATCH();
 131 }
 132
 133
 134 /* SURFACE_STATE for renderbuffer or texture surface (see
 135  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 136  */
 137 static uint32_t
 138 gen7_blorp_emit_surface_state(struct brw_context *brw,
 139                               const brw_blorp_surface_info *surface,
 140                               uint32_t read_domains, uint32_t write_domain,
 141                               bool is_render_target)
 142 {
 143    uint32_t wm_surf_offset;
 144    uint32_t width = surface->width;
 145    uint32_t height = surface->height;
 146    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 147     * color surfaces, width and height are measured in pixels; we don't need
 148     * to divide them by 2 as we do for Gen6 (see
 149     * gen6_blorp_emit_surface_state).
 150     */
 151    struct intel_mipmap_tree *mt = surface->mt;
 152    uint32_t tile_x, tile_y;
 153    const uint8_t mocs = GEN7_MOCS_L3;
 154
 155    uint32_t tiling = surface->map_stencil_as_y_tiled
 156       ? I915_TILING_Y : mt->tiling;
 157
 158    uint32_t *surf = (uint32_t *)
 159       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 160    memset(surf, 0, 8 * 4);
 161
 162    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 163              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 164              gen7_surface_tiling_mode(tiling);
 165
 166    if (surface->mt->valign == 4)
 167       surf[0] |= GEN7_SURFACE_VALIGN_4;
 168    if (surface->mt->halign == 8)
 169       surf[0] |= GEN7_SURFACE_HALIGN_8;
 170
 171    if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
 172       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 173    else
 174       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 175
 176    /* reloc */
 177    surf[1] =
 178       surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
 179
 180    /* Note that the low bits of these fields are missing, so
 181     * there's the possibility of getting in trouble.
 182     */
 183    assert(tile_x % 4 == 0);
 184    assert(tile_y % 2 == 0);
 185    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 186              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 187              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 188
 189    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 190              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 191
 192    uint32_t pitch_bytes = mt->pitch;
 193    if (surface->map_stencil_as_y_tiled)
 194       pitch_bytes *= 2;
 195    surf[3] = pitch_bytes - 1;
 196
 197    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 198    if (surface->mt->mcs_mt) {
 199       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 200                                 is_render_target);
 201    }
 202
 203    surf[7] = surface->mt->fast_clear_color_value;
 204
 205    if (brw->is_haswell) {
 206       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 207                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 208                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 209                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 210    }
 211
 212    /* Emit relocation to surface contents */
 213    drm_intel_bo_emit_reloc(brw->batch.bo,
 214                            wm_surf_offset + 4,
 215                            mt->bo,
 216                            surf[1] - mt->bo->offset64,
 217                            read_domains, write_domain);
 218
 219    gen7_check_surface_setup(surf, is_render_target);
 220
 221    return wm_surf_offset;
 222 }
 223
 224
 225 /* 3DSTATE_VS
 226  *
 227  * Disable vertex shader.
 228  */
 229 static void
 230 gen7_blorp_emit_vs_disable(struct brw_context *brw)
 231 {
 232    BEGIN_BATCH(7);
 233    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 234    OUT_BATCH(0);
 235    OUT_BATCH(0);
 236    OUT_BATCH(0);
 237    OUT_BATCH(0);
 238    OUT_BATCH(0);
 239    OUT_BATCH(0);
 240    ADVANCE_BATCH();
 241
 242    BEGIN_BATCH(6);
 243    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 244    OUT_BATCH(0);
 245    OUT_BATCH(0);
 246    OUT_BATCH(0);
 247    OUT_BATCH(0);
 248    OUT_BATCH(0);
 249    ADVANCE_BATCH();
 250 }
 251
 252
 253 /* 3DSTATE_HS
 254  *
 255  * Disable the hull shader.
 256  */
 257 static void
 258 gen7_blorp_emit_hs_disable(struct brw_context *brw)
 259 {
 260    BEGIN_BATCH(7);
 261    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 262    OUT_BATCH(0);
 263    OUT_BATCH(0);
 264    OUT_BATCH(0);
 265    OUT_BATCH(0);
 266    OUT_BATCH(0);
 267    OUT_BATCH(0);
 268    ADVANCE_BATCH();
 269
 270    BEGIN_BATCH(7);
 271    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 272    OUT_BATCH(0);
 273    OUT_BATCH(0);
 274    OUT_BATCH(0);
 275    OUT_BATCH(0);
 276    OUT_BATCH(0);
 277    OUT_BATCH(0);
 278    ADVANCE_BATCH();
 279 }
 280
 281
 282 /* 3DSTATE_TE
 283  *
 284  * Disable the tesselation engine.
 285  */
 286 static void
 287 gen7_blorp_emit_te_disable(struct brw_context *brw)
 288 {
 289    BEGIN_BATCH(4);
 290    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 291    OUT_BATCH(0);
 292    OUT_BATCH(0);
 293    OUT_BATCH(0);
 294    ADVANCE_BATCH();
 295 }
 296
 297
 298 /* 3DSTATE_DS
 299  *
 300  * Disable the domain shader.
 301  */
 302 static void
 303 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 304 {
 305    BEGIN_BATCH(7);
 306    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 307    OUT_BATCH(0);
 308    OUT_BATCH(0);
 309    OUT_BATCH(0);
 310    OUT_BATCH(0);
 311    OUT_BATCH(0);
 312    OUT_BATCH(0);
 313    ADVANCE_BATCH();
 314
 315    BEGIN_BATCH(6);
 316    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 317    OUT_BATCH(0);
 318    OUT_BATCH(0);
 319    OUT_BATCH(0);
 320    OUT_BATCH(0);
 321    OUT_BATCH(0);
 322    ADVANCE_BATCH();
 323 }
 324
 325 /* 3DSTATE_GS
 326  *
 327  * Disable the geometry shader.
 328  */
 329 static void
 330 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 331 {
 332    BEGIN_BATCH(7);
 333    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    OUT_BATCH(0);
 337    OUT_BATCH(0);
 338    OUT_BATCH(0);
 339    OUT_BATCH(0);
 340    ADVANCE_BATCH();
 341
 342    /**
 343     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 344     * Geometry > Geometry Shader > State:
 345     *
 346     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 347     *     whole fixed function pipeline when the GS enable changes value in
 348     *     the 3DSTATE_GS."
 349     *
 350     * The hardware architects have clarified that in this context "flush the
 351     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 352     * Stall" bit set.
 353     */
 354    if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 355       gen7_emit_cs_stall_flush(brw);
 356
 357    BEGIN_BATCH(7);
 358    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 359    OUT_BATCH(0);
 360    OUT_BATCH(0);
 361    OUT_BATCH(0);
 362    OUT_BATCH(0);
 363    OUT_BATCH(0);
 364    OUT_BATCH(0);
 365    ADVANCE_BATCH();
 366    brw->gs.enabled = false;
 367 }
 368
 369 /* 3DSTATE_STREAMOUT
 370  *
 371  * Disable streamout.
 372  */
 373 static void
 374 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 375 {
 376    BEGIN_BATCH(3);
 377    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 378    OUT_BATCH(0);
 379    OUT_BATCH(0);
 380    ADVANCE_BATCH();
 381 }
 382
 383
 384 static void
 385 gen7_blorp_emit_sf_config(struct brw_context *brw,
 386                           const brw_blorp_params *params)
 387 {
 388    /* 3DSTATE_SF
 389     *
 390     * Disable ViewportTransformEnable (dw1.1)
 391     *
 392     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 393     * Primitives Overview":
 394     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 395     *     use of screen- space coordinates).
 396     *
 397     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 398     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 399     *
 400     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 401     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 402     *     SOLID: Any triangle or rectangle object found to be front-facing
 403     *     is rendered as a solid object. This setting is required when
 404     *     (rendering rectangle (RECTLIST) objects.
 405     */
 406    {
 407       BEGIN_BATCH(7);
 408       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 409       OUT_BATCH(params->depth_format <<
 410                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 411       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 412       OUT_BATCH(0);
 413       OUT_BATCH(0);
 414       OUT_BATCH(0);
 415       OUT_BATCH(0);
 416       ADVANCE_BATCH();
 417    }
 418
 419    /* 3DSTATE_SBE */
 420    {
 421       BEGIN_BATCH(14);
 422       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 423       OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
 424                 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 425                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 426                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 427                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 428       for (int i = 0; i < 12; ++i)
 429          OUT_BATCH(0);
 430       ADVANCE_BATCH();
 431    }
 432 }
 433
 434
 435 /**
 436  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 437  */
 438 static void
 439 gen7_blorp_emit_wm_config(struct brw_context *brw,
 440                           const brw_blorp_params *params,
 441                           brw_blorp_prog_data *prog_data)
 442 {
 443    uint32_t dw1 = 0, dw2 = 0;
 444
 445    switch (params->hiz_op) {
 446    case GEN6_HIZ_OP_DEPTH_CLEAR:
 447       dw1 |= GEN7_WM_DEPTH_CLEAR;
 448       break;
 449    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 450       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 451       break;
 452    case GEN6_HIZ_OP_HIZ_RESOLVE:
 453       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 454       break;
 455    case GEN6_HIZ_OP_NONE:
 456       break;
 457    default:
 458       unreachable("not reached");
 459    }
 460    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 461    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 462    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 463    if (params->use_wm_prog) {
 464       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 465       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 466    }
 467
 468       if (params->dst.num_samples > 1) {
 469          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 470          if (prog_data && prog_data->persample_msaa_dispatch)
 471             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 472          else
 473             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 474       } else {
 475          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 476          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 477       }
 478
 479    BEGIN_BATCH(3);
 480    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 481    OUT_BATCH(dw1);
 482    OUT_BATCH(dw2);
 483    ADVANCE_BATCH();
 484 }
 485
 486
 487 /**
 488  * 3DSTATE_PS
 489  *
 490  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 491  * that, thread dispatch info must still be specified.
 492  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 493  *       valid range for this field is [0x3, 0x2f].
 494  *     - A dispatch mode must be given; that is, at least one of the
 495  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 496  *       discovered through simulator error messages.
 497  */
 498 static void
 499 gen7_blorp_emit_ps_config(struct brw_context *brw,
 500                           const brw_blorp_params *params,
 501                           uint32_t prog_offset,
 502                           brw_blorp_prog_data *prog_data)
 503 {
 504    uint32_t dw2, dw4, dw5;
 505    const int max_threads_shift = brw->is_haswell ?
 506       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 507
 508    dw2 = dw4 = dw5 = 0;
 509    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 510
 511    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 512     * what the program is compiled for.  If there isn't, then it shouldn't
 513     * matter because no program is actually being run.  However, the hardware
 514     * gets angry if we don't enable at least one dispatch mode, so just enable
 515     * 16-pixel dispatch unconditionally.
 516     */
 517    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 518
 519    if (brw->is_haswell)
 520       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 521    if (params->use_wm_prog) {
 522       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 523       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 524       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 525    }
 526
 527    BEGIN_BATCH(8);
 528    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 529    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 530    OUT_BATCH(dw2);
 531    OUT_BATCH(0);
 532    OUT_BATCH(dw4);
 533    OUT_BATCH(dw5);
 534    OUT_BATCH(0);
 535    OUT_BATCH(0);
 536    ADVANCE_BATCH();
 537 }
 538
 539
 540 static void
 541 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 542                                           uint32_t wm_bind_bo_offset)
 543 {
 544    BEGIN_BATCH(2);
 545    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 546    OUT_BATCH(wm_bind_bo_offset);
 547    ADVANCE_BATCH();
 548 }
 549
 550
 551 static void
 552 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 553                                           uint32_t sampler_offset)
 554 {
 555    BEGIN_BATCH(2);
 556    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 557    OUT_BATCH(sampler_offset);
 558    ADVANCE_BATCH();
 559 }
 560
 561
 562 static void
 563 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 564                             uint32_t wm_push_const_offset)
 565 {
 566    const uint8_t mocs = GEN7_MOCS_L3;
 567
 568    /* Make sure the push constants fill an exact integer number of
 569     * registers.
 570     */
 571    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 572
 573    /* There must be at least one register worth of push constant data. */
 574    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 575
 576    /* Enable push constant buffer 0. */
 577    BEGIN_BATCH(7);
 578    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 579              (7 - 2));
 580    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 581    OUT_BATCH(0);
 582    OUT_BATCH(wm_push_const_offset | mocs);
 583    OUT_BATCH(0);
 584    OUT_BATCH(0);
 585    OUT_BATCH(0);
 586    ADVANCE_BATCH();
 587 }
 588
 589 static void
 590 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 591 {
 592    BEGIN_BATCH(7);
 593    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 594    OUT_BATCH(0);
 595    OUT_BATCH(0);
 596    OUT_BATCH(0);
 597    OUT_BATCH(0);
 598    OUT_BATCH(0);
 599    OUT_BATCH(0);
 600    ADVANCE_BATCH();
 601 }
 602
 603 static void
 604 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 605                                      const brw_blorp_params *params)
 606 {
 607    const uint8_t mocs = GEN7_MOCS_L3;
 608    uint32_t surfwidth, surfheight;
 609    uint32_t surftype;
 610    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 611    unsigned int min_array_element;
 612    GLenum gl_target = params->depth.mt->target;
 613    unsigned int lod;
 614
 615    switch (gl_target) {
 616    case GL_TEXTURE_CUBE_MAP_ARRAY:
 617    case GL_TEXTURE_CUBE_MAP:
 618       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 619        * situation, but experiments show that gl_Layer doesn't work when we do
 620        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 621        * equivalent.
 622        */
 623       surftype = BRW_SURFACE_2D;
 624       depth *= 6;
 625       break;
 626    default:
 627       surftype = translate_tex_target(gl_target);
 628       break;
 629    }
 630
 631    min_array_element = params->depth.layer;
 632    if (params->depth.mt->num_samples > 1) {
 633       /* Convert physical layer to logical layer. */
 634       min_array_element /= params->depth.mt->num_samples;
 635    }
 636
 637    lod = params->depth.level - params->depth.mt->first_level;
 638
 639    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 640       /* HIZ ops for lod 0 may set the width & height a little
 641        * larger to allow the fast depth clear to fit the hardware
 642        * alignment requirements. (8x4)
 643        */
 644       surfwidth = params->depth.width;
 645       surfheight = params->depth.height;
 646    } else {
 647       surfwidth = params->depth.mt->logical_width0;
 648       surfheight = params->depth.mt->logical_height0;
 649    }
 650
 651    /* 3DSTATE_DEPTH_BUFFER */
 652    {
 653       brw_emit_depth_stall_flushes(brw);
 654
 655       BEGIN_BATCH(7);
 656       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 657       OUT_BATCH((params->depth.mt->pitch - 1) |
 658                 params->depth_format << 18 |
 659                 1 << 22 | /* hiz enable */
 660                 1 << 28 | /* depth write */
 661                 surftype << 29);
 662       OUT_RELOC(params->depth.mt->bo,
 663                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 664                 0);
 665       OUT_BATCH((surfwidth - 1) << 4 |
 666                 (surfheight - 1) << 18 |
 667                 lod);
 668       OUT_BATCH(((depth - 1) << 21) |
 669                 (min_array_element << 10) |
 670                 mocs);
 671       OUT_BATCH(0);
 672       OUT_BATCH((depth - 1) << 21);
 673       ADVANCE_BATCH();
 674    }
 675
 676    /* 3DSTATE_HIER_DEPTH_BUFFER */
 677    {
 678       struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 679
 680       BEGIN_BATCH(3);
 681       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 682       OUT_BATCH((mocs << 25) |
 683                 (hiz_buf->pitch - 1));
 684       OUT_RELOC(hiz_buf->bo,
 685                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 686                 0);
 687       ADVANCE_BATCH();
 688    }
 689
 690    /* 3DSTATE_STENCIL_BUFFER */
 691    {
 692       BEGIN_BATCH(3);
 693       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 694       OUT_BATCH(0);
 695       OUT_BATCH(0);
 696       ADVANCE_BATCH();
 697    }
 698 }
 699
 700
 701 static void
 702 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 703 {
 704    brw_emit_depth_stall_flushes(brw);
 705
 706    BEGIN_BATCH(7);
 707    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 708    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 709    OUT_BATCH(0);
 710    OUT_BATCH(0);
 711    OUT_BATCH(0);
 712    OUT_BATCH(0);
 713    OUT_BATCH(0);
 714    ADVANCE_BATCH();
 715
 716    BEGIN_BATCH(3);
 717    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 718    OUT_BATCH(0);
 719    OUT_BATCH(0);
 720    ADVANCE_BATCH();
 721
 722    BEGIN_BATCH(3);
 723    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 724    OUT_BATCH(0);
 725    OUT_BATCH(0);
 726    ADVANCE_BATCH();
 727 }
 728
 729
 730 /* 3DSTATE_CLEAR_PARAMS
 731  *
 732  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 733  * 3DSTATE_CLEAR_PARAMS:
 734  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 735  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 736  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 737  */
 738 static void
 739 gen7_blorp_emit_clear_params(struct brw_context *brw,
 740                              const brw_blorp_params *params)
 741 {
 742    BEGIN_BATCH(3);
 743    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 744    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 745    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 746    ADVANCE_BATCH();
 747 }
 748
 749
 750 /* 3DPRIMITIVE */
 751 static void
 752 gen7_blorp_emit_primitive(struct brw_context *brw,
 753                           const brw_blorp_params *params)
 754 {
 755    BEGIN_BATCH(7);
 756    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 757    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 758              _3DPRIM_RECTLIST);
 759    OUT_BATCH(3); /* vertex count per instance */
 760    OUT_BATCH(0);
 761    OUT_BATCH(params->num_layers); /* instance count */
 762    OUT_BATCH(0);
 763    OUT_BATCH(0);
 764    ADVANCE_BATCH();
 765 }
 766
 767
 768 /**
 769  * \copydoc gen6_blorp_exec()
 770  */
 771 void
 772 gen7_blorp_exec(struct brw_context *brw,
 773                 const brw_blorp_params *params)
 774 {
 775    if (brw->gen >= 8)
 776       return;
 777
 778    brw_blorp_prog_data *prog_data = NULL;
 779    uint32_t cc_blend_state_offset = 0;
 780    uint32_t cc_state_offset = 0;
 781    uint32_t depthstencil_offset;
 782    uint32_t wm_push_const_offset = 0;
 783    uint32_t wm_bind_bo_offset = 0;
 784    uint32_t sampler_offset = 0;
 785
 786    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 787    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 788    gen6_emit_3dstate_sample_mask(brw,
 789                                  params->dst.num_samples > 1 ?
 790                                  (1 << params->dst.num_samples) - 1 : 1);
 791    gen6_blorp_emit_state_base_address(brw, params);
 792    gen6_blorp_emit_vertices(brw, params);
 793    gen7_blorp_emit_urb_config(brw);
 794    if (params->use_wm_prog) {
 795       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 796       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 797       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 798       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 799    }
 800    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 801    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 802    if (brw->use_resource_streamer)
 803       gen7_disable_hw_binding_tables(brw);
 804    if (params->use_wm_prog) {
 805       uint32_t wm_surf_offset_renderbuffer;
 806       uint32_t wm_surf_offset_texture = 0;
 807       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 808       intel_miptree_used_for_rendering(params->dst.mt);
 809       wm_surf_offset_renderbuffer =
 810          gen7_blorp_emit_surface_state(brw, &params->dst,
 811                                        I915_GEM_DOMAIN_RENDER,
 812                                        I915_GEM_DOMAIN_RENDER,
 813                                        true /* is_render_target */);
 814       if (params->src.mt) {
 815          wm_surf_offset_texture =
 816             gen7_blorp_emit_surface_state(brw, &params->src,
 817                                           I915_GEM_DOMAIN_SAMPLER, 0,
 818                                           false /* is_render_target */);
 819       }
 820       wm_bind_bo_offset =
 821          gen6_blorp_emit_binding_table(brw,
 822                                        wm_surf_offset_renderbuffer,
 823                                        wm_surf_offset_texture);
 824       sampler_offset =
 825          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 826    }
 827    gen7_blorp_emit_vs_disable(brw);
 828    gen7_blorp_emit_hs_disable(brw);
 829    gen7_blorp_emit_te_disable(brw);
 830    gen7_blorp_emit_ds_disable(brw);
 831    gen7_blorp_emit_gs_disable(brw);
 832    gen7_blorp_emit_streamout_disable(brw);
 833    gen6_blorp_emit_clip_disable(brw);
 834    gen7_blorp_emit_sf_config(brw, params);
 835    gen7_blorp_emit_wm_config(brw, params, prog_data);
 836    if (params->use_wm_prog) {
 837       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 838       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 839       gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
 840    } else {
 841       gen7_blorp_emit_constant_ps_disable(brw);
 842    }
 843    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 844    gen7_blorp_emit_cc_viewport(brw);
 845
 846    if (params->depth.mt)
 847       gen7_blorp_emit_depth_stencil_config(brw, params);
 848    else
 849       gen7_blorp_emit_depth_disable(brw);
 850    gen7_blorp_emit_clear_params(brw, params);
 851    gen6_blorp_emit_drawing_rectangle(brw, params);
 852    gen7_blorp_emit_primitive(brw, params);
 853 }