2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen7_blorp.h"
43 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
44 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
46 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
47 * programmed in order for the programming of this state to be
51 gen7_blorp_emit_urb_config(struct brw_context
*brw
)
53 unsigned urb_size
= (brw
->is_haswell
&& brw
->gt
== 3) ? 32 : 16;
54 gen7_emit_push_constant_state(brw
,
55 urb_size
/ 2 /* vs_size */,
57 urb_size
/ 2 /* fs_size */);
59 /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
60 * 1.15:0 "VS Number of URB Entries".
62 gen7_emit_urb_state(brw
,
63 32 /* num_vs_entries */,
66 0 /* num_gs_entries */,
72 /* 3DSTATE_BLEND_STATE_POINTERS */
74 gen7_blorp_emit_blend_state_pointer(struct brw_context
*brw
,
75 uint32_t cc_blend_state_offset
)
78 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS
<< 16 | (2 - 2));
79 OUT_BATCH(cc_blend_state_offset
| 1);
84 /* 3DSTATE_CC_STATE_POINTERS */
86 gen7_blorp_emit_cc_state_pointer(struct brw_context
*brw
,
87 uint32_t cc_state_offset
)
90 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
91 OUT_BATCH(cc_state_offset
| 1);
96 gen7_blorp_emit_cc_viewport(struct brw_context
*brw
)
98 struct brw_cc_viewport
*ccv
;
99 uint32_t cc_vp_offset
;
101 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
104 ccv
->min_depth
= 0.0;
105 ccv
->max_depth
= 1.0;
108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC
<< 16 | (2 - 2));
109 OUT_BATCH(cc_vp_offset
);
114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context
*brw
,
120 uint32_t depthstencil_offset
)
123 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
<< 16 | (2 - 2));
124 OUT_BATCH(depthstencil_offset
| 1);
129 /* SURFACE_STATE for renderbuffer or texture surface (see
130 * brw_update_renderbuffer_surface and brw_update_texture_surface)
133 gen7_blorp_emit_surface_state(struct brw_context
*brw
,
134 const brw_blorp_surface_info
*surface
,
135 uint32_t read_domains
, uint32_t write_domain
,
136 bool is_render_target
)
138 uint32_t wm_surf_offset
;
139 uint32_t width
= surface
->width
;
140 uint32_t height
= surface
->height
;
141 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
142 * color surfaces, width and height are measured in pixels; we don't need
143 * to divide them by 2 as we do for Gen6 (see
144 * gen6_blorp_emit_surface_state).
146 struct intel_mipmap_tree
*mt
= surface
->mt
;
147 uint32_t tile_x
, tile_y
;
148 const uint8_t mocs
= GEN7_MOCS_L3
;
150 uint32_t tiling
= surface
->map_stencil_as_y_tiled
151 ? I915_TILING_Y
: mt
->tiling
;
153 uint32_t *surf
= (uint32_t *)
154 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32, &wm_surf_offset
);
155 memset(surf
, 0, 8 * 4);
157 surf
[0] = BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
158 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
|
159 gen7_surface_tiling_mode(tiling
);
161 if (surface
->mt
->align_h
== 4)
162 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
163 if (surface
->mt
->align_w
== 8)
164 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
166 if (surface
->array_layout
== ALL_SLICES_AT_EACH_LOD
)
167 surf
[0] |= GEN7_SURFACE_ARYSPC_LOD0
;
169 surf
[0] |= GEN7_SURFACE_ARYSPC_FULL
;
173 surface
->compute_tile_offsets(&tile_x
, &tile_y
) + mt
->bo
->offset64
;
175 /* Note that the low bits of these fields are missing, so
176 * there's the possibility of getting in trouble.
178 assert(tile_x
% 4 == 0);
179 assert(tile_y
% 2 == 0);
180 surf
[5] = SET_FIELD(tile_x
/ 4, BRW_SURFACE_X_OFFSET
) |
181 SET_FIELD(tile_y
/ 2, BRW_SURFACE_Y_OFFSET
) |
182 SET_FIELD(mocs
, GEN7_SURFACE_MOCS
);
184 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
185 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
187 uint32_t pitch_bytes
= mt
->pitch
;
188 if (surface
->map_stencil_as_y_tiled
)
190 surf
[3] = pitch_bytes
- 1;
192 surf
[4] = gen7_surface_msaa_bits(surface
->num_samples
, surface
->msaa_layout
);
193 if (surface
->mt
->mcs_mt
) {
194 gen7_set_surface_mcs_info(brw
, surf
, wm_surf_offset
, surface
->mt
->mcs_mt
,
198 surf
[7] = surface
->mt
->fast_clear_color_value
;
200 if (brw
->is_haswell
) {
201 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
202 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
203 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
204 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
207 /* Emit relocation to surface contents */
208 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
211 surf
[1] - mt
->bo
->offset64
,
212 read_domains
, write_domain
);
214 gen7_check_surface_setup(surf
, is_render_target
);
216 return wm_surf_offset
;
222 * Disable vertex shader.
225 gen7_blorp_emit_vs_disable(struct brw_context
*brw
)
228 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (7 - 2));
238 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
250 * Disable the hull shader.
253 gen7_blorp_emit_hs_disable(struct brw_context
*brw
)
256 OUT_BATCH(_3DSTATE_CONSTANT_HS
<< 16 | (7 - 2));
266 OUT_BATCH(_3DSTATE_HS
<< 16 | (7 - 2));
279 * Disable the tesselation engine.
282 gen7_blorp_emit_te_disable(struct brw_context
*brw
)
285 OUT_BATCH(_3DSTATE_TE
<< 16 | (4 - 2));
295 * Disable the domain shader.
298 gen7_blorp_emit_ds_disable(struct brw_context
*brw
)
301 OUT_BATCH(_3DSTATE_CONSTANT_DS
<< 16 | (7 - 2));
311 OUT_BATCH(_3DSTATE_DS
<< 16 | (6 - 2));
322 * Disable the geometry shader.
325 gen7_blorp_emit_gs_disable(struct brw_context
*brw
)
328 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (7 - 2));
338 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
339 * Geometry > Geometry Shader > State:
341 * "Note: Because of corruption in IVB:GT2, software needs to flush the
342 * whole fixed function pipeline when the GS enable changes value in
345 * The hardware architects have clarified that in this context "flush the
346 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
349 if (!brw
->is_haswell
&& brw
->gt
== 2 && brw
->gs
.enabled
)
350 gen7_emit_cs_stall_flush(brw
);
353 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
361 brw
->gs
.enabled
= false;
369 gen7_blorp_emit_streamout_disable(struct brw_context
*brw
)
372 OUT_BATCH(_3DSTATE_STREAMOUT
<< 16 | (3 - 2));
380 gen7_blorp_emit_sf_config(struct brw_context
*brw
,
381 const brw_blorp_params
*params
)
385 * Disable ViewportTransformEnable (dw1.1)
387 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
388 * Primitives Overview":
389 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
390 * use of screen- space coordinates).
392 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
393 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
395 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
396 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
397 * SOLID: Any triangle or rectangle object found to be front-facing
398 * is rendered as a solid object. This setting is required when
399 * (rendering rectangle (RECTLIST) objects.
403 OUT_BATCH(_3DSTATE_SF
<< 16 | (7 - 2));
404 OUT_BATCH(params
->depth_format
<<
405 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT
);
406 OUT_BATCH(params
->dst
.num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
417 OUT_BATCH(_3DSTATE_SBE
<< 16 | (14 - 2));
418 OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE
|
419 params
->num_varyings
<< GEN7_SBE_NUM_OUTPUTS_SHIFT
|
420 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT
|
421 BRW_SF_URB_ENTRY_READ_OFFSET
<<
422 GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT
);
423 for (int i
= 0; i
< 12; ++i
)
431 * Disable thread dispatch (dw5.19) and enable the HiZ op.
434 gen7_blorp_emit_wm_config(struct brw_context
*brw
,
435 const brw_blorp_params
*params
,
436 brw_blorp_prog_data
*prog_data
)
438 uint32_t dw1
= 0, dw2
= 0;
440 switch (params
->hiz_op
) {
441 case GEN6_HIZ_OP_DEPTH_CLEAR
:
442 dw1
|= GEN7_WM_DEPTH_CLEAR
;
444 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
445 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
447 case GEN6_HIZ_OP_HIZ_RESOLVE
:
448 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
450 case GEN6_HIZ_OP_NONE
:
453 unreachable("not reached");
455 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
456 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
457 dw1
|= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
458 if (params
->use_wm_prog
) {
459 dw1
|= GEN7_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
460 dw1
|= GEN7_WM_DISPATCH_ENABLE
; /* We are rendering */
463 if (params
->dst
.num_samples
> 1) {
464 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
465 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
466 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
468 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
470 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
471 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
475 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
485 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
486 * that, thread dispatch info must still be specified.
487 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
488 * valid range for this field is [0x3, 0x2f].
489 * - A dispatch mode must be given; that is, at least one of the
490 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
491 * discovered through simulator error messages.
494 gen7_blorp_emit_ps_config(struct brw_context
*brw
,
495 const brw_blorp_params
*params
,
496 uint32_t prog_offset
,
497 brw_blorp_prog_data
*prog_data
)
499 uint32_t dw2
, dw4
, dw5
;
500 const int max_threads_shift
= brw
->is_haswell
?
501 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
504 dw4
|= (brw
->max_wm_threads
- 1) << max_threads_shift
;
506 /* If there's a WM program, we need to do 16-pixel dispatch since that's
507 * what the program is compiled for. If there isn't, then it shouldn't
508 * matter because no program is actually being run. However, the hardware
509 * gets angry if we don't enable at least one dispatch mode, so just enable
510 * 16-pixel dispatch unconditionally.
512 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
515 dw4
|= SET_FIELD(1, HSW_PS_SAMPLE_MASK
); /* 1 sample for now */
516 if (params
->use_wm_prog
) {
517 dw2
|= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
518 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
519 dw5
|= prog_data
->first_curbe_grf
<< GEN7_PS_DISPATCH_START_GRF_SHIFT_0
;
523 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
524 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
536 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context
*brw
,
537 uint32_t wm_bind_bo_offset
)
540 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS
<< 16 | (2 - 2));
541 OUT_BATCH(wm_bind_bo_offset
);
547 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context
*brw
,
548 uint32_t sampler_offset
)
551 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
552 OUT_BATCH(sampler_offset
);
558 gen7_blorp_emit_constant_ps(struct brw_context
*brw
,
559 uint32_t wm_push_const_offset
)
561 const uint8_t mocs
= GEN7_MOCS_L3
;
563 /* Make sure the push constants fill an exact integer number of
566 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
568 /* There must be at least one register worth of push constant data. */
569 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
571 /* Enable push constant buffer 0. */
573 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
575 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS
);
577 OUT_BATCH(wm_push_const_offset
| mocs
);
585 gen7_blorp_emit_constant_ps_disable(struct brw_context
*brw
)
588 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (7 - 2));
599 gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
600 const brw_blorp_params
*params
)
602 const uint8_t mocs
= GEN7_MOCS_L3
;
603 uint32_t surfwidth
, surfheight
;
605 unsigned int depth
= MAX2(params
->depth
.mt
->logical_depth0
, 1);
606 unsigned int min_array_element
;
607 GLenum gl_target
= params
->depth
.mt
->target
;
611 case GL_TEXTURE_CUBE_MAP_ARRAY
:
612 case GL_TEXTURE_CUBE_MAP
:
613 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
614 * situation, but experiments show that gl_Layer doesn't work when we do
615 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
618 surftype
= BRW_SURFACE_2D
;
622 surftype
= translate_tex_target(gl_target
);
626 min_array_element
= params
->depth
.layer
;
627 if (params
->depth
.mt
->num_samples
> 1) {
628 /* Convert physical layer to logical layer. */
629 min_array_element
/= params
->depth
.mt
->num_samples
;
632 lod
= params
->depth
.level
- params
->depth
.mt
->first_level
;
634 if (params
->hiz_op
!= GEN6_HIZ_OP_NONE
&& lod
== 0) {
635 /* HIZ ops for lod 0 may set the width & height a little
636 * larger to allow the fast depth clear to fit the hardware
637 * alignment requirements. (8x4)
639 surfwidth
= params
->depth
.width
;
640 surfheight
= params
->depth
.height
;
642 surfwidth
= params
->depth
.mt
->logical_width0
;
643 surfheight
= params
->depth
.mt
->logical_height0
;
646 /* 3DSTATE_DEPTH_BUFFER */
648 brw_emit_depth_stall_flushes(brw
);
651 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
652 OUT_BATCH((params
->depth
.mt
->pitch
- 1) |
653 params
->depth_format
<< 18 |
654 1 << 22 | /* hiz enable */
655 1 << 28 | /* depth write */
657 OUT_RELOC(params
->depth
.mt
->bo
,
658 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
660 OUT_BATCH((surfwidth
- 1) << 4 |
661 (surfheight
- 1) << 18 |
663 OUT_BATCH(((depth
- 1) << 21) |
664 (min_array_element
<< 10) |
667 OUT_BATCH((depth
- 1) << 21);
671 /* 3DSTATE_HIER_DEPTH_BUFFER */
673 struct intel_miptree_aux_buffer
*hiz_buf
= params
->depth
.mt
->hiz_buf
;
676 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
677 OUT_BATCH((mocs
<< 25) |
678 (hiz_buf
->pitch
- 1));
679 OUT_RELOC(hiz_buf
->bo
,
680 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
685 /* 3DSTATE_STENCIL_BUFFER */
688 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
697 gen7_blorp_emit_depth_disable(struct brw_context
*brw
)
699 brw_emit_depth_stall_flushes(brw
);
702 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
703 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT
<< 18 | (BRW_SURFACE_NULL
<< 29));
712 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
718 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
725 /* 3DSTATE_CLEAR_PARAMS
727 * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
728 * 3DSTATE_CLEAR_PARAMS:
729 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along
730 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
731 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
734 gen7_blorp_emit_clear_params(struct brw_context
*brw
,
735 const brw_blorp_params
*params
)
738 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
739 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
740 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID
);
747 gen7_blorp_emit_primitive(struct brw_context
*brw
,
748 const brw_blorp_params
*params
)
751 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
752 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
|
754 OUT_BATCH(3); /* vertex count per instance */
756 OUT_BATCH(params
->num_layers
); /* instance count */
764 * \copydoc gen6_blorp_exec()
767 gen7_blorp_exec(struct brw_context
*brw
,
768 const brw_blorp_params
*params
)
773 brw_blorp_prog_data
*prog_data
= NULL
;
774 uint32_t cc_blend_state_offset
= 0;
775 uint32_t cc_state_offset
= 0;
776 uint32_t depthstencil_offset
;
777 uint32_t wm_push_const_offset
= 0;
778 uint32_t wm_bind_bo_offset
= 0;
779 uint32_t sampler_offset
= 0;
781 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
782 gen6_emit_3dstate_multisample(brw
, params
->dst
.num_samples
);
783 gen6_emit_3dstate_sample_mask(brw
,
784 params
->dst
.num_samples
> 1 ?
785 (1 << params
->dst
.num_samples
) - 1 : 1);
786 gen6_blorp_emit_state_base_address(brw
, params
);
787 gen6_blorp_emit_vertices(brw
, params
);
788 gen7_blorp_emit_urb_config(brw
);
789 if (params
->use_wm_prog
) {
790 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
791 cc_state_offset
= gen6_blorp_emit_cc_state(brw
);
792 gen7_blorp_emit_blend_state_pointer(brw
, cc_blend_state_offset
);
793 gen7_blorp_emit_cc_state_pointer(brw
, cc_state_offset
);
795 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
796 gen7_blorp_emit_depth_stencil_state_pointers(brw
, depthstencil_offset
);
797 if (brw
->use_resource_streamer
)
798 gen7_disable_hw_binding_tables(brw
);
799 if (params
->use_wm_prog
) {
800 uint32_t wm_surf_offset_renderbuffer
;
801 uint32_t wm_surf_offset_texture
= 0;
802 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
803 intel_miptree_used_for_rendering(params
->dst
.mt
);
804 wm_surf_offset_renderbuffer
=
805 gen7_blorp_emit_surface_state(brw
, ¶ms
->dst
,
806 I915_GEM_DOMAIN_RENDER
,
807 I915_GEM_DOMAIN_RENDER
,
808 true /* is_render_target */);
809 if (params
->src
.mt
) {
810 wm_surf_offset_texture
=
811 gen7_blorp_emit_surface_state(brw
, ¶ms
->src
,
812 I915_GEM_DOMAIN_SAMPLER
, 0,
813 false /* is_render_target */);
816 gen6_blorp_emit_binding_table(brw
,
817 wm_surf_offset_renderbuffer
,
818 wm_surf_offset_texture
);
820 gen6_blorp_emit_sampler_state(brw
, BRW_MAPFILTER_LINEAR
, 0, true);
822 gen7_blorp_emit_vs_disable(brw
);
823 gen7_blorp_emit_hs_disable(brw
);
824 gen7_blorp_emit_te_disable(brw
);
825 gen7_blorp_emit_ds_disable(brw
);
826 gen7_blorp_emit_gs_disable(brw
);
827 gen7_blorp_emit_streamout_disable(brw
);
828 gen6_blorp_emit_clip_disable(brw
);
829 gen7_blorp_emit_sf_config(brw
, params
);
830 gen7_blorp_emit_wm_config(brw
, params
, prog_data
);
831 if (params
->use_wm_prog
) {
832 gen7_blorp_emit_binding_table_pointers_ps(brw
, wm_bind_bo_offset
);
833 gen7_blorp_emit_sampler_state_pointers_ps(brw
, sampler_offset
);
834 gen7_blorp_emit_constant_ps(brw
, wm_push_const_offset
);
836 gen7_blorp_emit_constant_ps_disable(brw
);
838 gen7_blorp_emit_ps_config(brw
, params
, prog_offset
, prog_data
);
839 gen7_blorp_emit_cc_viewport(brw
);
841 if (params
->depth
.mt
)
842 gen7_blorp_emit_depth_stencil_config(brw
, params
);
844 gen7_blorp_emit_depth_disable(brw
);
845 gen7_blorp_emit_clear_params(brw
, params
);
846 gen6_blorp_emit_drawing_rectangle(brw
, params
);
847 gen7_blorp_emit_primitive(brw
, params
);