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[mesa.git] / src / mesa / drivers / dri / i965 / gen7_blorp.cpp
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25
26 #include "intel_batchbuffer.h"
27 #include "intel_mipmap_tree.h"
28
29 #include "brw_context.h"
30 #include "brw_state.h"
31
32 #include "brw_blorp.h"
33
34 static bool
35 gen7_blorp_skip_urb_config(const struct brw_context *brw)
36 {
37 if (brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE))
38 return false;
39
40 /* Vertex elements along with full VUE header take 96 bytes. As the size
41 * is expressed in 64 bytes, one needs at least two times that, otherwise
42 * the setup can be any valid configuration.
43 */
44 return brw->urb.vsize >= 2;
45 }
46
47 /* 3DSTATE_URB_VS
48 * 3DSTATE_URB_HS
49 * 3DSTATE_URB_DS
50 * 3DSTATE_URB_GS
51 *
52 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
53 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
54 *
55 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
56 * programmed in order for the programming of this state to be
57 * valid.
58 */
59 void
60 gen7_blorp_emit_urb_config(struct brw_context *brw)
61 {
62 /* URB allocations must be done in 8k chunks. */
63 const unsigned chunk_size_bytes = 8192;
64 const unsigned urb_size =
65 (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
66 const unsigned push_constant_bytes = 1024 * urb_size;
67 const unsigned push_constant_chunks =
68 push_constant_bytes / chunk_size_bytes;
69 const unsigned vs_size = 2;
70 const unsigned vs_start = push_constant_chunks;
71 const unsigned vs_chunks =
72 DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes);
73
74 if (gen7_blorp_skip_urb_config(brw))
75 return;
76
77 brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
78
79 gen7_emit_push_constant_state(brw,
80 urb_size / 2 /* vs_size */,
81 0 /* hs_size */,
82 0 /* ds_size */,
83 0 /* gs_size */,
84 urb_size / 2 /* fs_size */);
85
86 gen7_emit_urb_state(brw,
87 brw->urb.min_vs_entries /* num_vs_entries */,
88 vs_size,
89 vs_start,
90 0 /* num_hs_entries */,
91 1 /* hs_size */,
92 vs_start + vs_chunks /* hs_start */,
93 0 /* num_ds_entries */,
94 1 /* ds_size */,
95 vs_start + vs_chunks /* ds_start */,
96 0 /* num_gs_entries */,
97 1 /* gs_size */,
98 vs_start + vs_chunks /* gs_start */);
99 }
100
101
102 /* 3DSTATE_BLEND_STATE_POINTERS */
103 void
104 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
105 uint32_t cc_blend_state_offset)
106 {
107 BEGIN_BATCH(2);
108 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
109 OUT_BATCH(cc_blend_state_offset | 1);
110 ADVANCE_BATCH();
111 }
112
113
114 /* 3DSTATE_CC_STATE_POINTERS */
115 void
116 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
117 uint32_t cc_state_offset)
118 {
119 BEGIN_BATCH(2);
120 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
121 OUT_BATCH(cc_state_offset | 1);
122 ADVANCE_BATCH();
123 }
124
125 void
126 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
127 {
128 struct brw_cc_viewport *ccv;
129 uint32_t cc_vp_offset;
130
131 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
132 sizeof(*ccv), 32,
133 &cc_vp_offset);
134 ccv->min_depth = 0.0;
135 ccv->max_depth = 1.0;
136
137 BEGIN_BATCH(2);
138 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
139 OUT_BATCH(cc_vp_offset);
140 ADVANCE_BATCH();
141 }
142
143
144 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
145 *
146 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
147 */
148 static void
149 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
150 uint32_t depthstencil_offset)
151 {
152 BEGIN_BATCH(2);
153 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
154 OUT_BATCH(depthstencil_offset | 1);
155 ADVANCE_BATCH();
156 }
157
158
159 /* SURFACE_STATE for renderbuffer or texture surface (see
160 * brw_update_renderbuffer_surface and brw_update_texture_surface)
161 */
162 static uint32_t
163 gen7_blorp_emit_surface_state(struct brw_context *brw,
164 const brw_blorp_surface_info *surface,
165 uint32_t read_domains, uint32_t write_domain,
166 bool is_render_target)
167 {
168 uint32_t wm_surf_offset;
169 uint32_t width = surface->width;
170 uint32_t height = surface->height;
171 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
172 * color surfaces, width and height are measured in pixels; we don't need
173 * to divide them by 2 as we do for Gen6 (see
174 * gen6_blorp_emit_surface_state).
175 */
176 struct intel_mipmap_tree *mt = surface->mt;
177 uint32_t tile_x, tile_y;
178 const uint8_t mocs = GEN7_MOCS_L3;
179
180 uint32_t tiling = surface->map_stencil_as_y_tiled
181 ? I915_TILING_Y : mt->tiling;
182
183 uint32_t *surf = (uint32_t *)
184 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
185 memset(surf, 0, 8 * 4);
186
187 surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
188 surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
189 gen7_surface_tiling_mode(tiling);
190
191 if (surface->mt->valign == 4)
192 surf[0] |= GEN7_SURFACE_VALIGN_4;
193 if (surface->mt->halign == 8)
194 surf[0] |= GEN7_SURFACE_HALIGN_8;
195
196 if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
197 surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
198 else
199 surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
200
201 /* reloc */
202 surf[1] =
203 surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
204
205 /* Note that the low bits of these fields are missing, so
206 * there's the possibility of getting in trouble.
207 */
208 assert(tile_x % 4 == 0);
209 assert(tile_y % 2 == 0);
210 surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
211 SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
212 SET_FIELD(mocs, GEN7_SURFACE_MOCS);
213
214 surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
215 SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
216
217 uint32_t pitch_bytes = mt->pitch;
218 if (surface->map_stencil_as_y_tiled)
219 pitch_bytes *= 2;
220 surf[3] = pitch_bytes - 1;
221
222 surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
223 if (surface->mt->mcs_mt) {
224 gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
225 is_render_target);
226 }
227
228 surf[7] = surface->mt->fast_clear_color_value;
229
230 if (brw->is_haswell) {
231 surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
232 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
233 SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
234 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
235 }
236
237 /* Emit relocation to surface contents */
238 drm_intel_bo_emit_reloc(brw->batch.bo,
239 wm_surf_offset + 4,
240 mt->bo,
241 surf[1] - mt->bo->offset64,
242 read_domains, write_domain);
243
244 gen7_check_surface_setup(surf, is_render_target);
245
246 return wm_surf_offset;
247 }
248
249
250 /* 3DSTATE_VS
251 *
252 * Disable vertex shader.
253 */
254 static void
255 gen7_blorp_emit_vs_disable(struct brw_context *brw)
256 {
257 BEGIN_BATCH(7);
258 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
259 OUT_BATCH(0);
260 OUT_BATCH(0);
261 OUT_BATCH(0);
262 OUT_BATCH(0);
263 OUT_BATCH(0);
264 OUT_BATCH(0);
265 ADVANCE_BATCH();
266
267 BEGIN_BATCH(6);
268 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
269 OUT_BATCH(0);
270 OUT_BATCH(0);
271 OUT_BATCH(0);
272 OUT_BATCH(0);
273 OUT_BATCH(0);
274 ADVANCE_BATCH();
275 }
276
277
278 /* 3DSTATE_HS
279 *
280 * Disable the hull shader.
281 */
282 static void
283 gen7_blorp_emit_hs_disable(struct brw_context *brw)
284 {
285 BEGIN_BATCH(7);
286 OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
287 OUT_BATCH(0);
288 OUT_BATCH(0);
289 OUT_BATCH(0);
290 OUT_BATCH(0);
291 OUT_BATCH(0);
292 OUT_BATCH(0);
293 ADVANCE_BATCH();
294
295 BEGIN_BATCH(7);
296 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
297 OUT_BATCH(0);
298 OUT_BATCH(0);
299 OUT_BATCH(0);
300 OUT_BATCH(0);
301 OUT_BATCH(0);
302 OUT_BATCH(0);
303 ADVANCE_BATCH();
304 }
305
306
307 /* 3DSTATE_TE
308 *
309 * Disable the tesselation engine.
310 */
311 void
312 gen7_blorp_emit_te_disable(struct brw_context *brw)
313 {
314 BEGIN_BATCH(4);
315 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
316 OUT_BATCH(0);
317 OUT_BATCH(0);
318 OUT_BATCH(0);
319 ADVANCE_BATCH();
320 }
321
322
323 /* 3DSTATE_DS
324 *
325 * Disable the domain shader.
326 */
327 static void
328 gen7_blorp_emit_ds_disable(struct brw_context *brw)
329 {
330 BEGIN_BATCH(7);
331 OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
332 OUT_BATCH(0);
333 OUT_BATCH(0);
334 OUT_BATCH(0);
335 OUT_BATCH(0);
336 OUT_BATCH(0);
337 OUT_BATCH(0);
338 ADVANCE_BATCH();
339
340 BEGIN_BATCH(6);
341 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
342 OUT_BATCH(0);
343 OUT_BATCH(0);
344 OUT_BATCH(0);
345 OUT_BATCH(0);
346 OUT_BATCH(0);
347 ADVANCE_BATCH();
348 }
349
350 /* 3DSTATE_GS
351 *
352 * Disable the geometry shader.
353 */
354 static void
355 gen7_blorp_emit_gs_disable(struct brw_context *brw)
356 {
357 BEGIN_BATCH(7);
358 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
359 OUT_BATCH(0);
360 OUT_BATCH(0);
361 OUT_BATCH(0);
362 OUT_BATCH(0);
363 OUT_BATCH(0);
364 OUT_BATCH(0);
365 ADVANCE_BATCH();
366
367 /**
368 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
369 * Geometry > Geometry Shader > State:
370 *
371 * "Note: Because of corruption in IVB:GT2, software needs to flush the
372 * whole fixed function pipeline when the GS enable changes value in
373 * the 3DSTATE_GS."
374 *
375 * The hardware architects have clarified that in this context "flush the
376 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
377 * Stall" bit set.
378 */
379 if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
380 gen7_emit_cs_stall_flush(brw);
381
382 BEGIN_BATCH(7);
383 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
384 OUT_BATCH(0);
385 OUT_BATCH(0);
386 OUT_BATCH(0);
387 OUT_BATCH(0);
388 OUT_BATCH(0);
389 OUT_BATCH(0);
390 ADVANCE_BATCH();
391 brw->gs.enabled = false;
392 }
393
394 /* 3DSTATE_STREAMOUT
395 *
396 * Disable streamout.
397 */
398 static void
399 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
400 {
401 BEGIN_BATCH(3);
402 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
403 OUT_BATCH(0);
404 OUT_BATCH(0);
405 ADVANCE_BATCH();
406 }
407
408
409 static void
410 gen7_blorp_emit_sf_config(struct brw_context *brw,
411 const brw_blorp_params *params)
412 {
413 /* 3DSTATE_SF
414 *
415 * Disable ViewportTransformEnable (dw1.1)
416 *
417 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
418 * Primitives Overview":
419 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
420 * use of screen- space coordinates).
421 *
422 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
423 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
424 *
425 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
426 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
427 * SOLID: Any triangle or rectangle object found to be front-facing
428 * is rendered as a solid object. This setting is required when
429 * (rendering rectangle (RECTLIST) objects.
430 */
431 {
432 BEGIN_BATCH(7);
433 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
434 OUT_BATCH(params->depth_format <<
435 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
436 OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
437 OUT_BATCH(0);
438 OUT_BATCH(0);
439 OUT_BATCH(0);
440 OUT_BATCH(0);
441 ADVANCE_BATCH();
442 }
443
444 /* 3DSTATE_SBE */
445 {
446 BEGIN_BATCH(14);
447 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
448 OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
449 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
450 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
451 BRW_SF_URB_ENTRY_READ_OFFSET <<
452 GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
453 for (int i = 0; i < 12; ++i)
454 OUT_BATCH(0);
455 ADVANCE_BATCH();
456 }
457 }
458
459
460 /**
461 * Disable thread dispatch (dw5.19) and enable the HiZ op.
462 */
463 static void
464 gen7_blorp_emit_wm_config(struct brw_context *brw,
465 const brw_blorp_params *params,
466 brw_blorp_prog_data *prog_data)
467 {
468 uint32_t dw1 = 0, dw2 = 0;
469
470 switch (params->hiz_op) {
471 case GEN6_HIZ_OP_DEPTH_CLEAR:
472 dw1 |= GEN7_WM_DEPTH_CLEAR;
473 break;
474 case GEN6_HIZ_OP_DEPTH_RESOLVE:
475 dw1 |= GEN7_WM_DEPTH_RESOLVE;
476 break;
477 case GEN6_HIZ_OP_HIZ_RESOLVE:
478 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
479 break;
480 case GEN6_HIZ_OP_NONE:
481 break;
482 default:
483 unreachable("not reached");
484 }
485 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
486 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
487 dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
488
489 if (params->use_wm_prog)
490 dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
491
492 if (params->src.mt)
493 dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
494
495 if (params->dst.num_samples > 1) {
496 dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
497 if (prog_data && prog_data->persample_msaa_dispatch)
498 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
499 else
500 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
501 } else {
502 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
503 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
504 }
505
506 BEGIN_BATCH(3);
507 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
508 OUT_BATCH(dw1);
509 OUT_BATCH(dw2);
510 ADVANCE_BATCH();
511 }
512
513
514 /**
515 * 3DSTATE_PS
516 *
517 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
518 * that, thread dispatch info must still be specified.
519 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
520 * valid range for this field is [0x3, 0x2f].
521 * - A dispatch mode must be given; that is, at least one of the
522 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
523 * discovered through simulator error messages.
524 */
525 static void
526 gen7_blorp_emit_ps_config(struct brw_context *brw,
527 const brw_blorp_params *params,
528 uint32_t prog_offset,
529 brw_blorp_prog_data *prog_data)
530 {
531 uint32_t dw2, dw4, dw5;
532 const int max_threads_shift = brw->is_haswell ?
533 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
534
535 dw2 = dw4 = dw5 = 0;
536 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
537
538 /* If there's a WM program, we need to do 16-pixel dispatch since that's
539 * what the program is compiled for. If there isn't, then it shouldn't
540 * matter because no program is actually being run. However, the hardware
541 * gets angry if we don't enable at least one dispatch mode, so just enable
542 * 16-pixel dispatch unconditionally.
543 */
544 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
545
546 if (brw->is_haswell)
547 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
548 if (params->use_wm_prog) {
549 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
550 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
551 }
552
553 if (params->src.mt)
554 dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
555
556 dw4 |= params->fast_clear_op;
557
558 BEGIN_BATCH(8);
559 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
560 OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
561 OUT_BATCH(dw2);
562 OUT_BATCH(0);
563 OUT_BATCH(dw4);
564 OUT_BATCH(dw5);
565 OUT_BATCH(0);
566 OUT_BATCH(0);
567 ADVANCE_BATCH();
568 }
569
570
571 void
572 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
573 uint32_t wm_bind_bo_offset)
574 {
575 BEGIN_BATCH(2);
576 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
577 OUT_BATCH(wm_bind_bo_offset);
578 ADVANCE_BATCH();
579 }
580
581
582 void
583 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
584 uint32_t sampler_offset)
585 {
586 BEGIN_BATCH(2);
587 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
588 OUT_BATCH(sampler_offset);
589 ADVANCE_BATCH();
590 }
591
592
593 void
594 gen7_blorp_emit_constant_ps(struct brw_context *brw,
595 uint32_t wm_push_const_offset)
596 {
597 const uint8_t mocs = GEN7_MOCS_L3;
598
599 /* Make sure the push constants fill an exact integer number of
600 * registers.
601 */
602 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
603
604 /* There must be at least one register worth of push constant data. */
605 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
606
607 /* Enable push constant buffer 0. */
608 BEGIN_BATCH(7);
609 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
610 (7 - 2));
611 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
612 OUT_BATCH(0);
613 OUT_BATCH(wm_push_const_offset | mocs);
614 OUT_BATCH(0);
615 OUT_BATCH(0);
616 OUT_BATCH(0);
617 ADVANCE_BATCH();
618 }
619
620 void
621 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
622 {
623 BEGIN_BATCH(7);
624 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
625 OUT_BATCH(0);
626 OUT_BATCH(0);
627 OUT_BATCH(0);
628 OUT_BATCH(0);
629 OUT_BATCH(0);
630 OUT_BATCH(0);
631 ADVANCE_BATCH();
632 }
633
634 static void
635 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
636 const brw_blorp_params *params)
637 {
638 const uint8_t mocs = GEN7_MOCS_L3;
639 uint32_t surfwidth, surfheight;
640 uint32_t surftype;
641 unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
642 unsigned int min_array_element;
643 GLenum gl_target = params->depth.mt->target;
644 unsigned int lod;
645
646 switch (gl_target) {
647 case GL_TEXTURE_CUBE_MAP_ARRAY:
648 case GL_TEXTURE_CUBE_MAP:
649 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
650 * situation, but experiments show that gl_Layer doesn't work when we do
651 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
652 * equivalent.
653 */
654 surftype = BRW_SURFACE_2D;
655 depth *= 6;
656 break;
657 default:
658 surftype = translate_tex_target(gl_target);
659 break;
660 }
661
662 min_array_element = params->depth.layer;
663 if (params->depth.mt->num_samples > 1) {
664 /* Convert physical layer to logical layer. */
665 min_array_element /= params->depth.mt->num_samples;
666 }
667
668 lod = params->depth.level - params->depth.mt->first_level;
669
670 if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
671 /* HIZ ops for lod 0 may set the width & height a little
672 * larger to allow the fast depth clear to fit the hardware
673 * alignment requirements. (8x4)
674 */
675 surfwidth = params->depth.width;
676 surfheight = params->depth.height;
677 } else {
678 surfwidth = params->depth.mt->logical_width0;
679 surfheight = params->depth.mt->logical_height0;
680 }
681
682 /* 3DSTATE_DEPTH_BUFFER */
683 {
684 brw_emit_depth_stall_flushes(brw);
685
686 BEGIN_BATCH(7);
687 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
688 OUT_BATCH((params->depth.mt->pitch - 1) |
689 params->depth_format << 18 |
690 1 << 22 | /* hiz enable */
691 1 << 28 | /* depth write */
692 surftype << 29);
693 OUT_RELOC(params->depth.mt->bo,
694 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
695 0);
696 OUT_BATCH((surfwidth - 1) << 4 |
697 (surfheight - 1) << 18 |
698 lod);
699 OUT_BATCH(((depth - 1) << 21) |
700 (min_array_element << 10) |
701 mocs);
702 OUT_BATCH(0);
703 OUT_BATCH((depth - 1) << 21);
704 ADVANCE_BATCH();
705 }
706
707 /* 3DSTATE_HIER_DEPTH_BUFFER */
708 {
709 struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
710
711 BEGIN_BATCH(3);
712 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
713 OUT_BATCH((mocs << 25) |
714 (hiz_buf->pitch - 1));
715 OUT_RELOC(hiz_buf->bo,
716 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
717 0);
718 ADVANCE_BATCH();
719 }
720
721 /* 3DSTATE_STENCIL_BUFFER */
722 {
723 BEGIN_BATCH(3);
724 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
725 OUT_BATCH(0);
726 OUT_BATCH(0);
727 ADVANCE_BATCH();
728 }
729 }
730
731
732 static void
733 gen7_blorp_emit_depth_disable(struct brw_context *brw)
734 {
735 brw_emit_depth_stall_flushes(brw);
736
737 BEGIN_BATCH(7);
738 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
739 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
740 OUT_BATCH(0);
741 OUT_BATCH(0);
742 OUT_BATCH(0);
743 OUT_BATCH(0);
744 OUT_BATCH(0);
745 ADVANCE_BATCH();
746
747 BEGIN_BATCH(3);
748 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
749 OUT_BATCH(0);
750 OUT_BATCH(0);
751 ADVANCE_BATCH();
752
753 BEGIN_BATCH(3);
754 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
755 OUT_BATCH(0);
756 OUT_BATCH(0);
757 ADVANCE_BATCH();
758 }
759
760
761 /* 3DSTATE_CLEAR_PARAMS
762 *
763 * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
764 * 3DSTATE_CLEAR_PARAMS:
765 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along
766 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
767 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
768 */
769 void
770 gen7_blorp_emit_clear_params(struct brw_context *brw,
771 const brw_blorp_params *params)
772 {
773 BEGIN_BATCH(3);
774 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
775 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
776 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
777 ADVANCE_BATCH();
778 }
779
780
781 /* 3DPRIMITIVE */
782 void
783 gen7_blorp_emit_primitive(struct brw_context *brw,
784 const brw_blorp_params *params)
785 {
786 BEGIN_BATCH(7);
787 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
788 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
789 _3DPRIM_RECTLIST);
790 OUT_BATCH(3); /* vertex count per instance */
791 OUT_BATCH(0);
792 OUT_BATCH(params->num_layers); /* instance count */
793 OUT_BATCH(0);
794 OUT_BATCH(0);
795 ADVANCE_BATCH();
796 }
797
798
799 /**
800 * \copydoc gen6_blorp_exec()
801 */
802 void
803 gen7_blorp_exec(struct brw_context *brw,
804 const brw_blorp_params *params)
805 {
806 if (brw->gen >= 8)
807 return;
808
809 brw_blorp_prog_data *prog_data = NULL;
810 uint32_t cc_blend_state_offset = 0;
811 uint32_t cc_state_offset = 0;
812 uint32_t depthstencil_offset;
813 uint32_t wm_push_const_offset = 0;
814 uint32_t wm_bind_bo_offset = 0;
815
816 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
817 gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
818 gen6_emit_3dstate_sample_mask(brw,
819 params->dst.num_samples > 1 ?
820 (1 << params->dst.num_samples) - 1 : 1);
821 gen6_blorp_emit_state_base_address(brw, params);
822 gen6_blorp_emit_vertices(brw, params);
823 gen7_blorp_emit_urb_config(brw);
824 if (params->use_wm_prog) {
825 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
826 cc_state_offset = gen6_blorp_emit_cc_state(brw);
827 gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
828 gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
829 }
830 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
831 gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
832 if (brw->use_resource_streamer)
833 gen7_disable_hw_binding_tables(brw);
834 if (params->use_wm_prog) {
835 uint32_t wm_surf_offset_renderbuffer;
836 uint32_t wm_surf_offset_texture = 0;
837 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
838 intel_miptree_used_for_rendering(params->dst.mt);
839 wm_surf_offset_renderbuffer =
840 gen7_blorp_emit_surface_state(brw, &params->dst,
841 I915_GEM_DOMAIN_RENDER,
842 I915_GEM_DOMAIN_RENDER,
843 true /* is_render_target */);
844 if (params->src.mt) {
845 wm_surf_offset_texture =
846 gen7_blorp_emit_surface_state(brw, &params->src,
847 I915_GEM_DOMAIN_SAMPLER, 0,
848 false /* is_render_target */);
849 }
850 wm_bind_bo_offset =
851 gen6_blorp_emit_binding_table(brw,
852 wm_surf_offset_renderbuffer,
853 wm_surf_offset_texture);
854 }
855 gen7_blorp_emit_vs_disable(brw);
856 gen7_blorp_emit_hs_disable(brw);
857 gen7_blorp_emit_te_disable(brw);
858 gen7_blorp_emit_ds_disable(brw);
859 gen7_blorp_emit_gs_disable(brw);
860 gen7_blorp_emit_streamout_disable(brw);
861 gen6_blorp_emit_clip_disable(brw);
862 gen7_blorp_emit_sf_config(brw, params);
863 gen7_blorp_emit_wm_config(brw, params, prog_data);
864 if (params->use_wm_prog) {
865 gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
866 gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
867 } else {
868 gen7_blorp_emit_constant_ps_disable(brw);
869 }
870
871 if (params->src.mt) {
872 const uint32_t sampler_offset =
873 gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
874 gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
875 }
876
877 gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
878 gen7_blorp_emit_cc_viewport(brw);
879
880 if (params->depth.mt)
881 gen7_blorp_emit_depth_stencil_config(brw, params);
882 else
883 gen7_blorp_emit_depth_disable(brw);
884 gen7_blorp_emit_clear_params(brw, params);
885 gen6_blorp_emit_drawing_rectangle(brw, params);
886 gen7_blorp_emit_primitive(brw, params);
887 }