src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain,
 140                               bool is_render_target)
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    uint32_t wm_surf_offset;
 145    uint32_t width, height;
 146    surface->get_miplevel_dims(&width, &height);
 147    if (surface->map_stencil_as_y_tiled) {
 148       width *= 2;
 149       height /= 2;
 150    }
 151    struct intel_region *region = surface->mt->region;
 152
 153    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 154       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 155                       &wm_surf_offset);
 156    memset(surf, 0, sizeof(*surf));
 157
 158    if (surface->mt->align_h == 4)
 159       surf->ss0.vertical_alignment = 1;
 160    if (surface->mt->align_w == 8)
 161       surf->ss0.horizontal_alignment = 1;
 162
 163    surf->ss0.surface_format = surface->brw_surfaceformat;
 164    surf->ss0.surface_type = BRW_SURFACE_2D;
 165    surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
 166       GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
 167
 168    /* reloc */
 169    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 170
 171    surf->ss2.width = width - 1;
 172    surf->ss2.height = height - 1;
 173
 174    uint32_t tiling = surface->map_stencil_as_y_tiled
 175       ? I915_TILING_Y : region->tiling;
 176    gen7_set_surface_tiling(surf, tiling);
 177
 178    uint32_t pitch_bytes = region->pitch * region->cpp;
 179    if (surface->map_stencil_as_y_tiled)
 180       pitch_bytes *= 2;
 181    surf->ss3.pitch = pitch_bytes - 1;
 182
 183    gen7_set_surface_num_multisamples(surf, surface->num_samples);
 184
 185    if (intel->is_haswell) {
 186       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 187       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 188       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 189       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 190    }
 191
 192    /* Emit relocation to surface contents */
 193    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 194                            wm_surf_offset +
 195                            offsetof(struct gen7_surface_state, ss1),
 196                            region->bo,
 197                            surf->ss1.base_addr - region->bo->offset,
 198                            read_domains, write_domain);
 199
 200    gen7_check_surface_setup(surf, is_render_target);
 201
 202    return wm_surf_offset;
 203 }
 204
 205
 206 /**
 207  * SAMPLER_STATE.  See gen7_update_sampler_state().
 208  */
 209 static uint32_t
 210 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 211                               const brw_blorp_params *params)
 212 {
 213    uint32_t sampler_offset;
 214
 215    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 216       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 217                       sizeof(struct gen7_sampler_state),
 218                       32, &sampler_offset);
 219    memset(sampler, 0, sizeof(*sampler));
 220
 221    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 222    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 223    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 224
 225    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 226    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 227    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 228
 229    //   sampler->ss0.min_mag_neq = 1;
 230
 231    /* Set LOD bias:
 232     */
 233    sampler->ss0.lod_bias = 0;
 234
 235    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 236    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 237
 238    /* Set BaseMipLevel, MaxLOD, MinLOD:
 239     *
 240     * XXX: I don't think that using firstLevel, lastLevel works,
 241     * because we always setup the surface state as if firstLevel ==
 242     * level zero.  Probably have to subtract firstLevel from each of
 243     * these:
 244     */
 245    sampler->ss0.base_level = U_FIXED(0, 1);
 246
 247    sampler->ss1.max_lod = U_FIXED(0, 8);
 248    sampler->ss1.min_lod = U_FIXED(0, 8);
 249
 250    sampler->ss3.non_normalized_coord = 1;
 251
 252    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 253       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 254       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 255    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 256       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 257       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 258
 259    return sampler_offset;
 260 }
 261
 262
 263 /* 3DSTATE_HS
 264  *
 265  * Disable the hull shader.
 266  */
 267 static void
 268 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 269                            const brw_blorp_params *params)
 270 {
 271    struct intel_context *intel = &brw->intel;
 272
 273    BEGIN_BATCH(7);
 274    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 275    OUT_BATCH(0);
 276    OUT_BATCH(0);
 277    OUT_BATCH(0);
 278    OUT_BATCH(0);
 279    OUT_BATCH(0);
 280    OUT_BATCH(0);
 281    ADVANCE_BATCH();
 282 }
 283
 284
 285 /* 3DSTATE_TE
 286  *
 287  * Disable the tesselation engine.
 288  */
 289 static void
 290 gen7_blorp_emit_te_disable(struct brw_context *brw,
 291                            const brw_blorp_params *params)
 292 {
 293    struct intel_context *intel = &brw->intel;
 294
 295    BEGIN_BATCH(4);
 296    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    OUT_BATCH(0);
 300    ADVANCE_BATCH();
 301 }
 302
 303
 304 /* 3DSTATE_DS
 305  *
 306  * Disable the domain shader.
 307  */
 308 static void
 309 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 310                            const brw_blorp_params *params)
 311 {
 312    struct intel_context *intel = &brw->intel;
 313
 314    BEGIN_BATCH(6);
 315    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    OUT_BATCH(0);
 319    OUT_BATCH(0);
 320    OUT_BATCH(0);
 321    ADVANCE_BATCH();
 322 }
 323
 324
 325 /* 3DSTATE_STREAMOUT
 326  *
 327  * Disable streamout.
 328  */
 329 static void
 330 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 331                                   const brw_blorp_params *params)
 332 {
 333    struct intel_context *intel = &brw->intel;
 334
 335    BEGIN_BATCH(3);
 336    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 337    OUT_BATCH(0);
 338    OUT_BATCH(0);
 339    ADVANCE_BATCH();
 340 }
 341
 342
 343 static void
 344 gen7_blorp_emit_sf_config(struct brw_context *brw,
 345                           const brw_blorp_params *params)
 346 {
 347    struct intel_context *intel = &brw->intel;
 348
 349    /* 3DSTATE_SF
 350     *
 351     * Disable ViewportTransformEnable (dw1.1)
 352     *
 353     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 354     * Primitives Overview":
 355     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 356     *     use of screen- space coordinates).
 357     *
 358     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 359     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 360     *
 361     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 362     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 363     *     SOLID: Any triangle or rectangle object found to be front-facing
 364     *     is rendered as a solid object. This setting is required when
 365     *     (rendering rectangle (RECTLIST) objects.
 366     */
 367    {
 368       BEGIN_BATCH(7);
 369       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 370       OUT_BATCH(params->depth_format <<
 371                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 372       OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 373       OUT_BATCH(0);
 374       OUT_BATCH(0);
 375       OUT_BATCH(0);
 376       OUT_BATCH(0);
 377       ADVANCE_BATCH();
 378    }
 379
 380    /* 3DSTATE_SBE */
 381    {
 382       BEGIN_BATCH(14);
 383       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 384       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 385                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 386                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 387       for (int i = 0; i < 12; ++i)
 388          OUT_BATCH(0);
 389       ADVANCE_BATCH();
 390    }
 391 }
 392
 393
 394 /**
 395  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 396  */
 397 static void
 398 gen7_blorp_emit_wm_config(struct brw_context *brw,
 399                           const brw_blorp_params *params,
 400                           brw_blorp_prog_data *prog_data)
 401 {
 402    struct intel_context *intel = &brw->intel;
 403
 404    uint32_t dw1 = 0, dw2 = 0;
 405
 406    switch (params->hiz_op) {
 407    case GEN6_HIZ_OP_DEPTH_CLEAR:
 408       dw1 |= GEN7_WM_DEPTH_CLEAR;
 409       break;
 410    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 411       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 412       break;
 413    case GEN6_HIZ_OP_HIZ_RESOLVE:
 414       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 415       break;
 416    case GEN6_HIZ_OP_NONE:
 417       break;
 418    default:
 419       assert(0);
 420       break;
 421    }
 422    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 423    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 424    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 425    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 426    if (params->use_wm_prog) {
 427       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 428       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 429    }
 430
 431       if (params->num_samples > 0) {
 432          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 433          if (prog_data && prog_data->persample_msaa_dispatch)
 434             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 435          else
 436             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 437       } else {
 438          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 439          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 440       }
 441
 442    BEGIN_BATCH(3);
 443    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 444    OUT_BATCH(dw1);
 445    OUT_BATCH(dw2);
 446    ADVANCE_BATCH();
 447 }
 448
 449
 450 /**
 451  * 3DSTATE_PS
 452  *
 453  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 454  * that, thread dispatch info must still be specified.
 455  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 456  *       states that the valid range for this field is [0x3, 0x2f].
 457  *     - A dispatch mode must be given; that is, at least one of the
 458  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 459  *       discovered through simulator error messages.
 460  */
 461 static void
 462 gen7_blorp_emit_ps_config(struct brw_context *brw,
 463                           const brw_blorp_params *params,
 464                           uint32_t prog_offset,
 465                           brw_blorp_prog_data *prog_data)
 466 {
 467    struct intel_context *intel = &brw->intel;
 468    uint32_t dw2, dw4, dw5;
 469    const int max_threads_shift = brw->intel.is_haswell ?
 470       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 471
 472    dw2 = dw4 = dw5 = 0;
 473    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 474
 475    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 476     * what the program is compiled for.  If there isn't, then it shouldn't
 477     * matter because no program is actually being run.  However, the hardware
 478     * gets angry if we don't enable at least one dispatch mode, so just enable
 479     * 16-pixel dispatch unconditionally.
 480     */
 481    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 482
 483    if (intel->is_haswell)
 484       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 485    if (params->use_wm_prog) {
 486       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 487       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 488       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 489    }
 490
 491    BEGIN_BATCH(8);
 492    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 493    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 494    OUT_BATCH(dw2);
 495    OUT_BATCH(0);
 496    OUT_BATCH(dw4);
 497    OUT_BATCH(dw5);
 498    OUT_BATCH(0);
 499    OUT_BATCH(0);
 500    ADVANCE_BATCH();
 501 }
 502
 503
 504 static void
 505 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 506                                           const brw_blorp_params *params,
 507                                           uint32_t wm_bind_bo_offset)
 508 {
 509    struct intel_context *intel = &brw->intel;
 510
 511    BEGIN_BATCH(2);
 512    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 513    OUT_BATCH(wm_bind_bo_offset);
 514    ADVANCE_BATCH();
 515 }
 516
 517
 518 static void
 519 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 520                                           const brw_blorp_params *params,
 521                                           uint32_t sampler_offset)
 522 {
 523    struct intel_context *intel = &brw->intel;
 524
 525    BEGIN_BATCH(2);
 526    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 527    OUT_BATCH(sampler_offset);
 528    ADVANCE_BATCH();
 529 }
 530
 531
 532 static void
 533 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 534                             const brw_blorp_params *params,
 535                             uint32_t wm_push_const_offset)
 536 {
 537    struct intel_context *intel = &brw->intel;
 538
 539    /* Make sure the push constants fill an exact integer number of
 540     * registers.
 541     */
 542    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 543
 544    /* There must be at least one register worth of push constant data. */
 545    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 546
 547    /* Enable push constant buffer 0. */
 548    BEGIN_BATCH(7);
 549    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 550              (7 - 2));
 551    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 552    OUT_BATCH(0);
 553    OUT_BATCH(wm_push_const_offset);
 554    OUT_BATCH(0);
 555    OUT_BATCH(0);
 556    OUT_BATCH(0);
 557    ADVANCE_BATCH();
 558 }
 559
 560
 561 static void
 562 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 563                                      const brw_blorp_params *params)
 564 {
 565    struct intel_context *intel = &brw->intel;
 566    uint32_t draw_x, draw_y;
 567    uint32_t tile_mask_x, tile_mask_y;
 568
 569    if (params->depth.mt) {
 570       params->depth.get_draw_offsets(&draw_x, &draw_y);
 571       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 572    }
 573
 574    /* 3DSTATE_DEPTH_BUFFER */
 575    {
 576       uint32_t width, height;
 577       params->depth.get_miplevel_dims(&width, &height);
 578
 579       uint32_t tile_x = draw_x & tile_mask_x;
 580       uint32_t tile_y = draw_y & tile_mask_y;
 581       uint32_t offset =
 582          intel_region_get_aligned_offset(params->depth.mt->region,
 583                                          draw_x & ~tile_mask_x,
 584                                          draw_y & ~tile_mask_y);
 585
 586       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 587        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 588        * Coordinate Offset X/Y":
 589        *
 590        *   "The 3 LSBs of both offsets must be zero to ensure correct
 591        *   alignment"
 592        *
 593        * We have no guarantee that tile_x and tile_y are correctly aligned,
 594        * since they are determined by the mipmap layout, which is only aligned
 595        * to multiples of 4.
 596        *
 597        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 598        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 599        * up with a better solution.
 600        */
 601       tile_x &= ~7;
 602       tile_y &= ~7;
 603
 604       intel_emit_depth_stall_flushes(intel);
 605
 606       BEGIN_BATCH(7);
 607       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 608       uint32_t pitch_bytes =
 609          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 610       OUT_BATCH((pitch_bytes - 1) |
 611                 params->depth_format << 18 |
 612                 1 << 22 | /* hiz enable */
 613                 1 << 28 | /* depth write */
 614                 BRW_SURFACE_2D << 29);
 615       OUT_RELOC(params->depth.mt->region->bo,
 616                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 617                 offset);
 618       OUT_BATCH((width + tile_x - 1) << 4 |
 619                 (height + tile_y - 1) << 18);
 620       OUT_BATCH(0);
 621       OUT_BATCH(tile_x |
 622                 tile_y << 16);
 623       OUT_BATCH(0);
 624       ADVANCE_BATCH();
 625    }
 626
 627    /* 3DSTATE_HIER_DEPTH_BUFFER */
 628    {
 629       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 630       uint32_t hiz_offset =
 631          intel_region_get_aligned_offset(hiz_region,
 632                                          draw_x & ~tile_mask_x,
 633                                          (draw_y & ~tile_mask_y) / 2);
 634
 635       BEGIN_BATCH(3);
 636       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 637       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 638       OUT_RELOC(hiz_region->bo,
 639                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 640                 hiz_offset);
 641       ADVANCE_BATCH();
 642    }
 643
 644    /* 3DSTATE_STENCIL_BUFFER */
 645    {
 646       BEGIN_BATCH(3);
 647       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 648       OUT_BATCH(0);
 649       OUT_BATCH(0);
 650       ADVANCE_BATCH();
 651    }
 652 }
 653
 654
 655 static void
 656 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 657                               const brw_blorp_params *params)
 658 {
 659    struct intel_context *intel = &brw->intel;
 660
 661    BEGIN_BATCH(7);
 662    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 663    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 664    OUT_BATCH(0);
 665    OUT_BATCH(0);
 666    OUT_BATCH(0);
 667    OUT_BATCH(0);
 668    OUT_BATCH(0);
 669    ADVANCE_BATCH();
 670 }
 671
 672
 673 /* 3DSTATE_CLEAR_PARAMS
 674  *
 675  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 676  * 3DSTATE_CLEAR_PARAMS:
 677  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 678  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 679  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 680  */
 681 static void
 682 gen7_blorp_emit_clear_params(struct brw_context *brw,
 683                              const brw_blorp_params *params)
 684 {
 685    struct intel_context *intel = &brw->intel;
 686
 687    BEGIN_BATCH(3);
 688    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 689    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 690    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 691    ADVANCE_BATCH();
 692 }
 693
 694
 695 /* 3DPRIMITIVE */
 696 static void
 697 gen7_blorp_emit_primitive(struct brw_context *brw,
 698                           const brw_blorp_params *params)
 699 {
 700    struct intel_context *intel = &brw->intel;
 701
 702    BEGIN_BATCH(7);
 703    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 704    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 705              _3DPRIM_RECTLIST);
 706    OUT_BATCH(3); /* vertex count per instance */
 707    OUT_BATCH(0);
 708    OUT_BATCH(1); /* instance count */
 709    OUT_BATCH(0);
 710    OUT_BATCH(0);
 711    ADVANCE_BATCH();
 712 }
 713
 714
 715 /**
 716  * \copydoc gen6_blorp_exec()
 717  */
 718 void
 719 gen7_blorp_exec(struct intel_context *intel,
 720                 const brw_blorp_params *params)
 721 {
 722    struct gl_context *ctx = &intel->ctx;
 723    struct brw_context *brw = brw_context(ctx);
 724    brw_blorp_prog_data *prog_data = NULL;
 725    uint32_t cc_blend_state_offset = 0;
 726    uint32_t cc_state_offset = 0;
 727    uint32_t depthstencil_offset;
 728    uint32_t wm_push_const_offset = 0;
 729    uint32_t wm_bind_bo_offset = 0;
 730    uint32_t sampler_offset = 0;
 731
 732    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 733    gen6_blorp_emit_batch_head(brw, params);
 734    gen7_allocate_push_constants(brw);
 735    gen6_emit_3dstate_multisample(brw, params->num_samples);
 736    gen6_emit_3dstate_sample_mask(brw, params->num_samples);
 737    gen6_blorp_emit_state_base_address(brw, params);
 738    gen6_blorp_emit_vertices(brw, params);
 739    gen7_blorp_emit_urb_config(brw, params);
 740    if (params->use_wm_prog) {
 741       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 742       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 743       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 744       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 745    }
 746    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 747    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 748                                                 depthstencil_offset);
 749    if (params->use_wm_prog) {
 750       uint32_t wm_surf_offset_renderbuffer;
 751       uint32_t wm_surf_offset_texture;
 752       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 753       wm_surf_offset_renderbuffer =
 754          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 755                                        I915_GEM_DOMAIN_RENDER,
 756                                        I915_GEM_DOMAIN_RENDER,
 757                                        true /* is_render_target */);
 758       wm_surf_offset_texture =
 759          gen7_blorp_emit_surface_state(brw, params, &params->src,
 760                                        I915_GEM_DOMAIN_SAMPLER, 0,
 761                                        false /* is_render_target */);
 762       wm_bind_bo_offset =
 763          gen6_blorp_emit_binding_table(brw, params,
 764                                        wm_surf_offset_renderbuffer,
 765                                        wm_surf_offset_texture);
 766       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 767    }
 768    gen6_blorp_emit_vs_disable(brw, params);
 769    gen7_blorp_emit_hs_disable(brw, params);
 770    gen7_blorp_emit_te_disable(brw, params);
 771    gen7_blorp_emit_ds_disable(brw, params);
 772    gen6_blorp_emit_gs_disable(brw, params);
 773    gen7_blorp_emit_streamout_disable(brw, params);
 774    gen6_blorp_emit_clip_disable(brw, params);
 775    gen7_blorp_emit_sf_config(brw, params);
 776    gen7_blorp_emit_wm_config(brw, params, prog_data);
 777    if (params->use_wm_prog) {
 778       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 779                                                 wm_bind_bo_offset);
 780       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 781       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 782    }
 783    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 784    gen7_blorp_emit_cc_viewport(brw, params);
 785
 786    if (params->depth.mt)
 787       gen7_blorp_emit_depth_stencil_config(brw, params);
 788    else
 789       gen7_blorp_emit_depth_disable(brw, params);
 790    gen7_blorp_emit_clear_params(brw, params);
 791    gen6_blorp_emit_drawing_rectangle(brw, params);
 792    gen7_blorp_emit_primitive(brw, params);
 793
 794    /* See comments above at first invocation of intel_flush() in
 795     * gen6_blorp_emit_batch_head().
 796     */
 797    intel_flush(ctx);
 798
 799    /* Be safe. */
 800    brw->state.dirty.brw = ~0;
 801    brw->state.dirty.cache = ~0;
 802 }