src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain,
 140                               bool is_render_target)
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    uint32_t wm_surf_offset;
 145    uint32_t width, height;
 146    surface->get_miplevel_dims(&width, &height);
 147    if (surface->num_samples > 0) { /* TODO: wrong for 8x */
 148       width /= 2;
 149       height /= 2;
 150    }
 151    if (surface->map_stencil_as_y_tiled) {
 152       width *= 2;
 153       height /= 2;
 154    }
 155    struct intel_region *region = surface->mt->region;
 156
 157    /* TODO: handle other formats */
 158    uint32_t format = surface->map_stencil_as_y_tiled
 159       ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 160
 161    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 162       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 163                       &wm_surf_offset);
 164    memset(surf, 0, sizeof(*surf));
 165
 166    if (surface->mt->align_h == 4)
 167       surf->ss0.vertical_alignment = 1;
 168    if (surface->mt->align_w == 8)
 169       surf->ss0.horizontal_alignment = 1;
 170
 171    surf->ss0.surface_format = format;
 172    surf->ss0.surface_type = BRW_SURFACE_2D;
 173    surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
 174       GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
 175
 176    /* reloc */
 177    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 178
 179    surf->ss2.width = width - 1;
 180    surf->ss2.height = height - 1;
 181
 182    uint32_t tiling = surface->map_stencil_as_y_tiled
 183       ? I915_TILING_Y : region->tiling;
 184    gen7_set_surface_tiling(surf, tiling);
 185
 186    uint32_t pitch_bytes = region->pitch * region->cpp;
 187    if (surface->map_stencil_as_y_tiled)
 188       pitch_bytes *= 2;
 189    surf->ss3.pitch = pitch_bytes - 1;
 190
 191    gen7_set_surface_num_multisamples(surf, surface->num_samples);
 192
 193    if (intel->is_haswell) {
 194       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 195       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 196       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 197       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 198    }
 199
 200    /* Emit relocation to surface contents */
 201    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 202                            wm_surf_offset +
 203                            offsetof(struct gen7_surface_state, ss1),
 204                            region->bo,
 205                            surf->ss1.base_addr - region->bo->offset,
 206                            read_domains, write_domain);
 207
 208    gen7_check_surface_setup(surf, is_render_target);
 209
 210    return wm_surf_offset;
 211 }
 212
 213
 214 /**
 215  * SAMPLER_STATE.  See gen7_update_sampler_state().
 216  */
 217 static uint32_t
 218 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 219                               const brw_blorp_params *params)
 220 {
 221    uint32_t sampler_offset;
 222
 223    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 224       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 225                       sizeof(struct gen7_sampler_state),
 226                       32, &sampler_offset);
 227    memset(sampler, 0, sizeof(*sampler));
 228
 229    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 230    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 231    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 232
 233    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 234    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 235    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 236
 237    //   sampler->ss0.min_mag_neq = 1;
 238
 239    /* Set LOD bias:
 240     */
 241    sampler->ss0.lod_bias = 0;
 242
 243    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 244    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 245
 246    /* Set BaseMipLevel, MaxLOD, MinLOD:
 247     *
 248     * XXX: I don't think that using firstLevel, lastLevel works,
 249     * because we always setup the surface state as if firstLevel ==
 250     * level zero.  Probably have to subtract firstLevel from each of
 251     * these:
 252     */
 253    sampler->ss0.base_level = U_FIXED(0, 1);
 254
 255    sampler->ss1.max_lod = U_FIXED(0, 8);
 256    sampler->ss1.min_lod = U_FIXED(0, 8);
 257
 258    sampler->ss3.non_normalized_coord = 1;
 259
 260    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 261       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 262       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 263    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 264       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 265       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 266
 267    return sampler_offset;
 268 }
 269
 270
 271 /* 3DSTATE_HS
 272  *
 273  * Disable the hull shader.
 274  */
 275 static void
 276 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 277                            const brw_blorp_params *params)
 278 {
 279    struct intel_context *intel = &brw->intel;
 280
 281    BEGIN_BATCH(7);
 282    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 283    OUT_BATCH(0);
 284    OUT_BATCH(0);
 285    OUT_BATCH(0);
 286    OUT_BATCH(0);
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    ADVANCE_BATCH();
 290 }
 291
 292
 293 /* 3DSTATE_TE
 294  *
 295  * Disable the tesselation engine.
 296  */
 297 static void
 298 gen7_blorp_emit_te_disable(struct brw_context *brw,
 299                            const brw_blorp_params *params)
 300 {
 301    struct intel_context *intel = &brw->intel;
 302
 303    BEGIN_BATCH(4);
 304    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 305    OUT_BATCH(0);
 306    OUT_BATCH(0);
 307    OUT_BATCH(0);
 308    ADVANCE_BATCH();
 309 }
 310
 311
 312 /* 3DSTATE_DS
 313  *
 314  * Disable the domain shader.
 315  */
 316 static void
 317 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 318                            const brw_blorp_params *params)
 319 {
 320    struct intel_context *intel = &brw->intel;
 321
 322    BEGIN_BATCH(6);
 323    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    ADVANCE_BATCH();
 330 }
 331
 332
 333 /* 3DSTATE_STREAMOUT
 334  *
 335  * Disable streamout.
 336  */
 337 static void
 338 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 339                                   const brw_blorp_params *params)
 340 {
 341    struct intel_context *intel = &brw->intel;
 342
 343    BEGIN_BATCH(3);
 344    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 345    OUT_BATCH(0);
 346    OUT_BATCH(0);
 347    ADVANCE_BATCH();
 348 }
 349
 350
 351 static void
 352 gen7_blorp_emit_sf_config(struct brw_context *brw,
 353                           const brw_blorp_params *params)
 354 {
 355    struct intel_context *intel = &brw->intel;
 356
 357    /* 3DSTATE_SF
 358     *
 359     * Disable ViewportTransformEnable (dw1.1)
 360     *
 361     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 362     * Primitives Overview":
 363     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 364     *     use of screen- space coordinates).
 365     *
 366     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 367     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 368     *
 369     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 370     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 371     *     SOLID: Any triangle or rectangle object found to be front-facing
 372     *     is rendered as a solid object. This setting is required when
 373     *     (rendering rectangle (RECTLIST) objects.
 374     */
 375    {
 376       BEGIN_BATCH(7);
 377       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 378       OUT_BATCH(params->depth_format <<
 379                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 380       OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 381       OUT_BATCH(0);
 382       OUT_BATCH(0);
 383       OUT_BATCH(0);
 384       OUT_BATCH(0);
 385       ADVANCE_BATCH();
 386    }
 387
 388    /* 3DSTATE_SBE */
 389    {
 390       BEGIN_BATCH(14);
 391       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 392       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 393                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 394                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 395       for (int i = 0; i < 12; ++i)
 396          OUT_BATCH(0);
 397       ADVANCE_BATCH();
 398    }
 399 }
 400
 401
 402 /**
 403  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 404  */
 405 static void
 406 gen7_blorp_emit_wm_config(struct brw_context *brw,
 407                           const brw_blorp_params *params,
 408                           brw_blorp_prog_data *prog_data)
 409 {
 410    struct intel_context *intel = &brw->intel;
 411
 412    uint32_t dw1 = 0, dw2 = 0;
 413
 414    switch (params->hiz_op) {
 415    case GEN6_HIZ_OP_DEPTH_CLEAR:
 416       dw1 |= GEN7_WM_DEPTH_CLEAR;
 417       break;
 418    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 419       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 420       break;
 421    case GEN6_HIZ_OP_HIZ_RESOLVE:
 422       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 423       break;
 424    case GEN6_HIZ_OP_NONE:
 425       break;
 426    default:
 427       assert(0);
 428       break;
 429    }
 430    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 431    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 432    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 433    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 434    if (params->use_wm_prog) {
 435       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 436       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 437    }
 438
 439       if (params->num_samples > 0) {
 440          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 441          if (prog_data && prog_data->persample_msaa_dispatch)
 442             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 443          else
 444             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 445       } else {
 446          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 447          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 448       }
 449
 450    BEGIN_BATCH(3);
 451    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 452    OUT_BATCH(dw1);
 453    OUT_BATCH(dw2);
 454    ADVANCE_BATCH();
 455 }
 456
 457
 458 /**
 459  * 3DSTATE_PS
 460  *
 461  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 462  * that, thread dispatch info must still be specified.
 463  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 464  *       states that the valid range for this field is [0x3, 0x2f].
 465  *     - A dispatch mode must be given; that is, at least one of the
 466  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 467  *       discovered through simulator error messages.
 468  */
 469 static void
 470 gen7_blorp_emit_ps_config(struct brw_context *brw,
 471                           const brw_blorp_params *params,
 472                           uint32_t prog_offset,
 473                           brw_blorp_prog_data *prog_data)
 474 {
 475    struct intel_context *intel = &brw->intel;
 476    uint32_t dw2, dw4, dw5;
 477    const int max_threads_shift = brw->intel.is_haswell ?
 478       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 479
 480    dw2 = dw4 = dw5 = 0;
 481    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 482
 483    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 484     * what the program is compiled for.  If there isn't, then it shouldn't
 485     * matter because no program is actually being run.  However, the hardware
 486     * gets angry if we don't enable at least one dispatch mode, so just enable
 487     * 16-pixel dispatch unconditionally.
 488     */
 489    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 490
 491    if (intel->is_haswell)
 492       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 493    if (params->use_wm_prog) {
 494       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 495       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 496       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 497    }
 498
 499    BEGIN_BATCH(8);
 500    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 501    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 502    OUT_BATCH(dw2);
 503    OUT_BATCH(0);
 504    OUT_BATCH(dw4);
 505    OUT_BATCH(dw5);
 506    OUT_BATCH(0);
 507    OUT_BATCH(0);
 508    ADVANCE_BATCH();
 509 }
 510
 511
 512 static void
 513 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 514                                           const brw_blorp_params *params,
 515                                           uint32_t wm_bind_bo_offset)
 516 {
 517    struct intel_context *intel = &brw->intel;
 518
 519    BEGIN_BATCH(2);
 520    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 521    OUT_BATCH(wm_bind_bo_offset);
 522    ADVANCE_BATCH();
 523 }
 524
 525
 526 static void
 527 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 528                                           const brw_blorp_params *params,
 529                                           uint32_t sampler_offset)
 530 {
 531    struct intel_context *intel = &brw->intel;
 532
 533    BEGIN_BATCH(2);
 534    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 535    OUT_BATCH(sampler_offset);
 536    ADVANCE_BATCH();
 537 }
 538
 539
 540 static void
 541 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 542                             const brw_blorp_params *params,
 543                             uint32_t wm_push_const_offset)
 544 {
 545    struct intel_context *intel = &brw->intel;
 546
 547    /* Make sure the push constants fill an exact integer number of
 548     * registers.
 549     */
 550    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 551
 552    /* There must be at least one register worth of push constant data. */
 553    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 554
 555    /* Enable push constant buffer 0. */
 556    BEGIN_BATCH(7);
 557    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 558              (7 - 2));
 559    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 560    OUT_BATCH(0);
 561    OUT_BATCH(wm_push_const_offset);
 562    OUT_BATCH(0);
 563    OUT_BATCH(0);
 564    OUT_BATCH(0);
 565    ADVANCE_BATCH();
 566 }
 567
 568
 569 static void
 570 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 571                                      const brw_blorp_params *params)
 572 {
 573    struct intel_context *intel = &brw->intel;
 574    uint32_t draw_x, draw_y;
 575    uint32_t tile_mask_x, tile_mask_y;
 576
 577    if (params->depth.mt) {
 578       params->depth.get_draw_offsets(&draw_x, &draw_y);
 579       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 580    }
 581
 582    /* 3DSTATE_DEPTH_BUFFER */
 583    {
 584       uint32_t width, height;
 585       params->depth.get_miplevel_dims(&width, &height);
 586
 587       uint32_t tile_x = draw_x & tile_mask_x;
 588       uint32_t tile_y = draw_y & tile_mask_y;
 589       uint32_t offset =
 590          intel_region_get_aligned_offset(params->depth.mt->region,
 591                                          draw_x & ~tile_mask_x,
 592                                          draw_y & ~tile_mask_y);
 593
 594       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 595        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 596        * Coordinate Offset X/Y":
 597        *
 598        *   "The 3 LSBs of both offsets must be zero to ensure correct
 599        *   alignment"
 600        *
 601        * We have no guarantee that tile_x and tile_y are correctly aligned,
 602        * since they are determined by the mipmap layout, which is only aligned
 603        * to multiples of 4.
 604        *
 605        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 606        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 607        * up with a better solution.
 608        */
 609       tile_x &= ~7;
 610       tile_y &= ~7;
 611
 612       intel_emit_depth_stall_flushes(intel);
 613
 614       BEGIN_BATCH(7);
 615       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 616       uint32_t pitch_bytes =
 617          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 618       OUT_BATCH((pitch_bytes - 1) |
 619                 params->depth_format << 18 |
 620                 1 << 22 | /* hiz enable */
 621                 1 << 28 | /* depth write */
 622                 BRW_SURFACE_2D << 29);
 623       OUT_RELOC(params->depth.mt->region->bo,
 624                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 625                 offset);
 626       OUT_BATCH((width + tile_x - 1) << 4 |
 627                 (height + tile_y - 1) << 18);
 628       OUT_BATCH(0);
 629       OUT_BATCH(tile_x |
 630                 tile_y << 16);
 631       OUT_BATCH(0);
 632       ADVANCE_BATCH();
 633    }
 634
 635    /* 3DSTATE_HIER_DEPTH_BUFFER */
 636    {
 637       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 638       uint32_t hiz_offset =
 639          intel_region_get_aligned_offset(hiz_region,
 640                                          draw_x & ~tile_mask_x,
 641                                          (draw_y & ~tile_mask_y) / 2);
 642
 643       BEGIN_BATCH(3);
 644       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 645       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 646       OUT_RELOC(hiz_region->bo,
 647                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 648                 hiz_offset);
 649       ADVANCE_BATCH();
 650    }
 651
 652    /* 3DSTATE_STENCIL_BUFFER */
 653    {
 654       BEGIN_BATCH(3);
 655       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 656       OUT_BATCH(0);
 657       OUT_BATCH(0);
 658       ADVANCE_BATCH();
 659    }
 660 }
 661
 662
 663 static void
 664 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 665                               const brw_blorp_params *params)
 666 {
 667    struct intel_context *intel = &brw->intel;
 668
 669    BEGIN_BATCH(7);
 670    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 671    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 672    OUT_BATCH(0);
 673    OUT_BATCH(0);
 674    OUT_BATCH(0);
 675    OUT_BATCH(0);
 676    OUT_BATCH(0);
 677    ADVANCE_BATCH();
 678 }
 679
 680
 681 /* 3DSTATE_CLEAR_PARAMS
 682  *
 683  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 684  * 3DSTATE_CLEAR_PARAMS:
 685  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 686  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 687  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 688  */
 689 static void
 690 gen7_blorp_emit_clear_params(struct brw_context *brw,
 691                              const brw_blorp_params *params)
 692 {
 693    struct intel_context *intel = &brw->intel;
 694
 695    BEGIN_BATCH(3);
 696    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 697    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 698    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 699    ADVANCE_BATCH();
 700 }
 701
 702
 703 /* 3DPRIMITIVE */
 704 static void
 705 gen7_blorp_emit_primitive(struct brw_context *brw,
 706                           const brw_blorp_params *params)
 707 {
 708    struct intel_context *intel = &brw->intel;
 709
 710    BEGIN_BATCH(7);
 711    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 712    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 713              _3DPRIM_RECTLIST);
 714    OUT_BATCH(3); /* vertex count per instance */
 715    OUT_BATCH(0);
 716    OUT_BATCH(1); /* instance count */
 717    OUT_BATCH(0);
 718    OUT_BATCH(0);
 719    ADVANCE_BATCH();
 720 }
 721
 722
 723 /**
 724  * \copydoc gen6_blorp_exec()
 725  */
 726 void
 727 gen7_blorp_exec(struct intel_context *intel,
 728                 const brw_blorp_params *params)
 729 {
 730    struct gl_context *ctx = &intel->ctx;
 731    struct brw_context *brw = brw_context(ctx);
 732    brw_blorp_prog_data *prog_data = NULL;
 733    uint32_t cc_blend_state_offset = 0;
 734    uint32_t cc_state_offset = 0;
 735    uint32_t depthstencil_offset;
 736    uint32_t wm_push_const_offset = 0;
 737    uint32_t wm_bind_bo_offset = 0;
 738    uint32_t sampler_offset = 0;
 739
 740    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 741    gen6_blorp_emit_batch_head(brw, params);
 742    gen7_allocate_push_constants(brw);
 743    gen6_emit_3dstate_multisample(brw, params->num_samples);
 744    gen6_emit_3dstate_sample_mask(brw, params->num_samples);
 745    gen6_blorp_emit_state_base_address(brw, params);
 746    gen6_blorp_emit_vertices(brw, params);
 747    gen7_blorp_emit_urb_config(brw, params);
 748    if (params->use_wm_prog) {
 749       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 750       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 751       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 752       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 753    }
 754    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 755    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 756                                                 depthstencil_offset);
 757    if (params->use_wm_prog) {
 758       uint32_t wm_surf_offset_renderbuffer;
 759       uint32_t wm_surf_offset_texture;
 760       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 761       wm_surf_offset_renderbuffer =
 762          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 763                                        I915_GEM_DOMAIN_RENDER,
 764                                        I915_GEM_DOMAIN_RENDER,
 765                                        true /* is_render_target */);
 766       wm_surf_offset_texture =
 767          gen7_blorp_emit_surface_state(brw, params, &params->src,
 768                                        I915_GEM_DOMAIN_SAMPLER, 0,
 769                                        false /* is_render_target */);
 770       wm_bind_bo_offset =
 771          gen6_blorp_emit_binding_table(brw, params,
 772                                        wm_surf_offset_renderbuffer,
 773                                        wm_surf_offset_texture);
 774       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 775    }
 776    gen6_blorp_emit_vs_disable(brw, params);
 777    gen7_blorp_emit_hs_disable(brw, params);
 778    gen7_blorp_emit_te_disable(brw, params);
 779    gen7_blorp_emit_ds_disable(brw, params);
 780    gen6_blorp_emit_gs_disable(brw, params);
 781    gen7_blorp_emit_streamout_disable(brw, params);
 782    gen6_blorp_emit_clip_disable(brw, params);
 783    gen7_blorp_emit_sf_config(brw, params);
 784    gen7_blorp_emit_wm_config(brw, params, prog_data);
 785    if (params->use_wm_prog) {
 786       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 787                                                 wm_bind_bo_offset);
 788       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 789       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 790    }
 791    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 792    gen7_blorp_emit_cc_viewport(brw, params);
 793
 794    if (params->depth.mt)
 795       gen7_blorp_emit_depth_stencil_config(brw, params);
 796    else
 797       gen7_blorp_emit_depth_disable(brw, params);
 798    gen7_blorp_emit_clear_params(brw, params);
 799    gen6_blorp_emit_drawing_rectangle(brw, params);
 800    gen7_blorp_emit_primitive(brw, params);
 801
 802    /* See comments above at first invocation of intel_flush() in
 803     * gen6_blorp_emit_batch_head().
 804     */
 805    intel_flush(ctx);
 806
 807    /* Be safe. */
 808    brw->state.dirty.brw = ~0;
 809    brw->state.dirty.cache = ~0;
 810 }