src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    BEGIN_BATCH(2);
  71    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  72    OUT_BATCH(cc_blend_state_offset | 1);
  73    ADVANCE_BATCH();
  74 }
  75
  76
  77 /* 3DSTATE_CC_STATE_POINTERS */
  78 static void
  79 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  80                                  const brw_blorp_params *params,
  81                                  uint32_t cc_state_offset)
  82 {
  83    BEGIN_BATCH(2);
  84    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  85    OUT_BATCH(cc_state_offset | 1);
  86    ADVANCE_BATCH();
  87 }
  88
  89 static void
  90 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  91                             const brw_blorp_params *params)
  92 {
  93    struct brw_cc_viewport *ccv;
  94    uint32_t cc_vp_offset;
  95
  96    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
  97                                                    sizeof(*ccv), 32,
  98                                                    &cc_vp_offset);
  99    ccv->min_depth = 0.0;
 100    ccv->max_depth = 1.0;
 101
 102    BEGIN_BATCH(2);
 103    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 104    OUT_BATCH(cc_vp_offset);
 105    ADVANCE_BATCH();
 106 }
 107
 108
 109 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 110  *
 111  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 112  */
 113 static void
 114 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 115                                              const brw_blorp_params *params,
 116                                              uint32_t depthstencil_offset)
 117 {
 118    BEGIN_BATCH(2);
 119    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 120    OUT_BATCH(depthstencil_offset | 1);
 121    ADVANCE_BATCH();
 122 }
 123
 124
 125 /* SURFACE_STATE for renderbuffer or texture surface (see
 126  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 127  */
 128 static uint32_t
 129 gen7_blorp_emit_surface_state(struct brw_context *brw,
 130                               const brw_blorp_params *params,
 131                               const brw_blorp_surface_info *surface,
 132                               uint32_t read_domains, uint32_t write_domain,
 133                               bool is_render_target)
 134 {
 135    struct intel_context *intel = &brw->intel;
 136
 137    uint32_t wm_surf_offset;
 138    uint32_t width = surface->width;
 139    uint32_t height = surface->height;
 140    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 141     * color surfaces, width and height are measured in pixels; we don't need
 142     * to divide them by 2 as we do for Gen6 (see
 143     * gen6_blorp_emit_surface_state).
 144     */
 145    struct intel_region *region = surface->mt->region;
 146    uint32_t tile_x, tile_y;
 147
 148    uint32_t tiling = surface->map_stencil_as_y_tiled
 149       ? I915_TILING_Y : region->tiling;
 150
 151    uint32_t *surf = (uint32_t *)
 152       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 153    memset(surf, 0, 8 * 4);
 154
 155    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 156              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 157              gen7_surface_tiling_mode(tiling);
 158
 159    if (surface->mt->align_h == 4)
 160       surf[0] |= GEN7_SURFACE_VALIGN_4;
 161    if (surface->mt->align_w == 8)
 162       surf[0] |= GEN7_SURFACE_HALIGN_8;
 163
 164    if (surface->array_spacing_lod0)
 165       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 166    else
 167       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 168
 169    /* reloc */
 170    surf[1] =
 171       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 172
 173    /* Note that the low bits of these fields are missing, so
 174     * there's the possibility of getting in trouble.
 175     */
 176    assert(tile_x % 4 == 0);
 177    assert(tile_y % 2 == 0);
 178    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 179              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 180
 181    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 182              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 183
 184    uint32_t pitch_bytes = region->pitch;
 185    if (surface->map_stencil_as_y_tiled)
 186       pitch_bytes *= 2;
 187    surf[3] = pitch_bytes - 1;
 188
 189    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 190    if (surface->mt->mcs_mt) {
 191       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 192                                 is_render_target);
 193    }
 194
 195    surf[7] = surface->mt->fast_clear_color_value;
 196
 197    if (intel->is_haswell) {
 198       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 199                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 200                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 201                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 202    }
 203
 204    /* Emit relocation to surface contents */
 205    drm_intel_bo_emit_reloc(brw->batch.bo,
 206                            wm_surf_offset + 4,
 207                            region->bo,
 208                            surf[1] - region->bo->offset,
 209                            read_domains, write_domain);
 210
 211    gen7_check_surface_setup(surf, is_render_target);
 212
 213    return wm_surf_offset;
 214 }
 215
 216
 217 /**
 218  * SAMPLER_STATE.  See gen7_update_sampler_state().
 219  */
 220 static uint32_t
 221 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 222                               const brw_blorp_params *params)
 223 {
 224    uint32_t sampler_offset;
 225
 226    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 227       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 228                       sizeof(struct gen7_sampler_state),
 229                       32, &sampler_offset);
 230    memset(sampler, 0, sizeof(*sampler));
 231
 232    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 233    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 234    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 235
 236    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 237    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 238    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 239
 240    //   sampler->ss0.min_mag_neq = 1;
 241
 242    /* Set LOD bias:
 243     */
 244    sampler->ss0.lod_bias = 0;
 245
 246    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 247    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 248
 249    /* Set BaseMipLevel, MaxLOD, MinLOD:
 250     *
 251     * XXX: I don't think that using firstLevel, lastLevel works,
 252     * because we always setup the surface state as if firstLevel ==
 253     * level zero.  Probably have to subtract firstLevel from each of
 254     * these:
 255     */
 256    sampler->ss0.base_level = U_FIXED(0, 1);
 257
 258    sampler->ss1.max_lod = U_FIXED(0, 8);
 259    sampler->ss1.min_lod = U_FIXED(0, 8);
 260
 261    sampler->ss3.non_normalized_coord = 1;
 262
 263    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 264       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 265       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 266    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 267       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 268       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 269
 270    return sampler_offset;
 271 }
 272
 273
 274 /* 3DSTATE_VS
 275  *
 276  * Disable vertex shader.
 277  */
 278 static void
 279 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 280                            const brw_blorp_params *params)
 281 {
 282    BEGIN_BATCH(7);
 283    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 284    OUT_BATCH(0);
 285    OUT_BATCH(0);
 286    OUT_BATCH(0);
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    OUT_BATCH(0);
 290    ADVANCE_BATCH();
 291
 292    BEGIN_BATCH(6);
 293    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    ADVANCE_BATCH();
 300 }
 301
 302
 303 /* 3DSTATE_HS
 304  *
 305  * Disable the hull shader.
 306  */
 307 static void
 308 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 309                            const brw_blorp_params *params)
 310 {
 311    BEGIN_BATCH(7);
 312    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    OUT_BATCH(0);
 319    ADVANCE_BATCH();
 320
 321    BEGIN_BATCH(7);
 322    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    ADVANCE_BATCH();
 330 }
 331
 332
 333 /* 3DSTATE_TE
 334  *
 335  * Disable the tesselation engine.
 336  */
 337 static void
 338 gen7_blorp_emit_te_disable(struct brw_context *brw,
 339                            const brw_blorp_params *params)
 340 {
 341    BEGIN_BATCH(4);
 342    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 343    OUT_BATCH(0);
 344    OUT_BATCH(0);
 345    OUT_BATCH(0);
 346    ADVANCE_BATCH();
 347 }
 348
 349
 350 /* 3DSTATE_DS
 351  *
 352  * Disable the domain shader.
 353  */
 354 static void
 355 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 356                            const brw_blorp_params *params)
 357 {
 358    BEGIN_BATCH(7);
 359    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 360    OUT_BATCH(0);
 361    OUT_BATCH(0);
 362    OUT_BATCH(0);
 363    OUT_BATCH(0);
 364    OUT_BATCH(0);
 365    OUT_BATCH(0);
 366    ADVANCE_BATCH();
 367
 368    BEGIN_BATCH(6);
 369    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 370    OUT_BATCH(0);
 371    OUT_BATCH(0);
 372    OUT_BATCH(0);
 373    OUT_BATCH(0);
 374    OUT_BATCH(0);
 375    ADVANCE_BATCH();
 376 }
 377
 378 /* 3DSTATE_GS
 379  *
 380  * Disable the geometry shader.
 381  */
 382 static void
 383 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 384                            const brw_blorp_params *params)
 385 {
 386    BEGIN_BATCH(7);
 387    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 388    OUT_BATCH(0);
 389    OUT_BATCH(0);
 390    OUT_BATCH(0);
 391    OUT_BATCH(0);
 392    OUT_BATCH(0);
 393    OUT_BATCH(0);
 394    ADVANCE_BATCH();
 395
 396    BEGIN_BATCH(7);
 397    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 398    OUT_BATCH(0);
 399    OUT_BATCH(0);
 400    OUT_BATCH(0);
 401    OUT_BATCH(0);
 402    OUT_BATCH(0);
 403    OUT_BATCH(0);
 404    ADVANCE_BATCH();
 405 }
 406
 407 /* 3DSTATE_STREAMOUT
 408  *
 409  * Disable streamout.
 410  */
 411 static void
 412 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 413                                   const brw_blorp_params *params)
 414 {
 415    BEGIN_BATCH(3);
 416    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 417    OUT_BATCH(0);
 418    OUT_BATCH(0);
 419    ADVANCE_BATCH();
 420 }
 421
 422
 423 static void
 424 gen7_blorp_emit_sf_config(struct brw_context *brw,
 425                           const brw_blorp_params *params)
 426 {
 427    /* 3DSTATE_SF
 428     *
 429     * Disable ViewportTransformEnable (dw1.1)
 430     *
 431     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 432     * Primitives Overview":
 433     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 434     *     use of screen- space coordinates).
 435     *
 436     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 437     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 438     *
 439     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 440     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 441     *     SOLID: Any triangle or rectangle object found to be front-facing
 442     *     is rendered as a solid object. This setting is required when
 443     *     (rendering rectangle (RECTLIST) objects.
 444     */
 445    {
 446       BEGIN_BATCH(7);
 447       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 448       OUT_BATCH(params->depth_format <<
 449                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 450       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 451       OUT_BATCH(0);
 452       OUT_BATCH(0);
 453       OUT_BATCH(0);
 454       OUT_BATCH(0);
 455       ADVANCE_BATCH();
 456    }
 457
 458    /* 3DSTATE_SBE */
 459    {
 460       BEGIN_BATCH(14);
 461       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 462       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 463                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 464                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 465       for (int i = 0; i < 12; ++i)
 466          OUT_BATCH(0);
 467       ADVANCE_BATCH();
 468    }
 469 }
 470
 471
 472 /**
 473  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 474  */
 475 static void
 476 gen7_blorp_emit_wm_config(struct brw_context *brw,
 477                           const brw_blorp_params *params,
 478                           brw_blorp_prog_data *prog_data)
 479 {
 480    uint32_t dw1 = 0, dw2 = 0;
 481
 482    switch (params->hiz_op) {
 483    case GEN6_HIZ_OP_DEPTH_CLEAR:
 484       dw1 |= GEN7_WM_DEPTH_CLEAR;
 485       break;
 486    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 487       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 488       break;
 489    case GEN6_HIZ_OP_HIZ_RESOLVE:
 490       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 491       break;
 492    case GEN6_HIZ_OP_NONE:
 493       break;
 494    default:
 495       assert(0);
 496       break;
 497    }
 498    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 499    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 500    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 501    if (params->use_wm_prog) {
 502       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 503       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 504    }
 505
 506       if (params->num_samples > 1) {
 507          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 508          if (prog_data && prog_data->persample_msaa_dispatch)
 509             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 510          else
 511             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 512       } else {
 513          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 514          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 515       }
 516
 517    BEGIN_BATCH(3);
 518    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 519    OUT_BATCH(dw1);
 520    OUT_BATCH(dw2);
 521    ADVANCE_BATCH();
 522 }
 523
 524
 525 /**
 526  * 3DSTATE_PS
 527  *
 528  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 529  * that, thread dispatch info must still be specified.
 530  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 531  *       states that the valid range for this field is [0x3, 0x2f].
 532  *     - A dispatch mode must be given; that is, at least one of the
 533  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 534  *       discovered through simulator error messages.
 535  */
 536 static void
 537 gen7_blorp_emit_ps_config(struct brw_context *brw,
 538                           const brw_blorp_params *params,
 539                           uint32_t prog_offset,
 540                           brw_blorp_prog_data *prog_data)
 541 {
 542    struct intel_context *intel = &brw->intel;
 543    uint32_t dw2, dw4, dw5;
 544    const int max_threads_shift = brw->intel.is_haswell ?
 545       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 546
 547    dw2 = dw4 = dw5 = 0;
 548    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 549
 550    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 551     * what the program is compiled for.  If there isn't, then it shouldn't
 552     * matter because no program is actually being run.  However, the hardware
 553     * gets angry if we don't enable at least one dispatch mode, so just enable
 554     * 16-pixel dispatch unconditionally.
 555     */
 556    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 557
 558    if (intel->is_haswell)
 559       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 560    if (params->use_wm_prog) {
 561       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 562       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 563       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 564    }
 565
 566    switch (params->fast_clear_op) {
 567    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 568       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 569       break;
 570    case GEN7_FAST_CLEAR_OP_RESOLVE:
 571       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 572       break;
 573    default:
 574       break;
 575    }
 576
 577    BEGIN_BATCH(8);
 578    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 579    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 580    OUT_BATCH(dw2);
 581    OUT_BATCH(0);
 582    OUT_BATCH(dw4);
 583    OUT_BATCH(dw5);
 584    OUT_BATCH(0);
 585    OUT_BATCH(0);
 586    ADVANCE_BATCH();
 587 }
 588
 589
 590 static void
 591 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 592                                           const brw_blorp_params *params,
 593                                           uint32_t wm_bind_bo_offset)
 594 {
 595    BEGIN_BATCH(2);
 596    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 597    OUT_BATCH(wm_bind_bo_offset);
 598    ADVANCE_BATCH();
 599 }
 600
 601
 602 static void
 603 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 604                                           const brw_blorp_params *params,
 605                                           uint32_t sampler_offset)
 606 {
 607    BEGIN_BATCH(2);
 608    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 609    OUT_BATCH(sampler_offset);
 610    ADVANCE_BATCH();
 611 }
 612
 613
 614 static void
 615 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 616                             const brw_blorp_params *params,
 617                             uint32_t wm_push_const_offset)
 618 {
 619    /* Make sure the push constants fill an exact integer number of
 620     * registers.
 621     */
 622    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 623
 624    /* There must be at least one register worth of push constant data. */
 625    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 626
 627    /* Enable push constant buffer 0. */
 628    BEGIN_BATCH(7);
 629    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 630              (7 - 2));
 631    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 632    OUT_BATCH(0);
 633    OUT_BATCH(wm_push_const_offset);
 634    OUT_BATCH(0);
 635    OUT_BATCH(0);
 636    OUT_BATCH(0);
 637    ADVANCE_BATCH();
 638 }
 639
 640 static void
 641 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 642                                     const brw_blorp_params *params)
 643 {
 644    BEGIN_BATCH(7);
 645    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 646    OUT_BATCH(0);
 647    OUT_BATCH(0);
 648    OUT_BATCH(0);
 649    OUT_BATCH(0);
 650    OUT_BATCH(0);
 651    OUT_BATCH(0);
 652    ADVANCE_BATCH();
 653 }
 654
 655 static void
 656 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 657                                      const brw_blorp_params *params)
 658 {
 659    struct gl_context *ctx = &brw->intel.ctx;
 660    uint32_t draw_x = params->depth.x_offset;
 661    uint32_t draw_y = params->depth.y_offset;
 662    uint32_t tile_mask_x, tile_mask_y;
 663
 664    brw_get_depthstencil_tile_masks(params->depth.mt,
 665                                    params->depth.level,
 666                                    params->depth.layer,
 667                                    NULL,
 668                                    &tile_mask_x, &tile_mask_y);
 669
 670    /* 3DSTATE_DEPTH_BUFFER */
 671    {
 672       uint32_t tile_x = draw_x & tile_mask_x;
 673       uint32_t tile_y = draw_y & tile_mask_y;
 674       uint32_t offset =
 675          intel_region_get_aligned_offset(params->depth.mt->region,
 676                                          draw_x & ~tile_mask_x,
 677                                          draw_y & ~tile_mask_y, false);
 678
 679       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 680        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 681        * Coordinate Offset X/Y":
 682        *
 683        *   "The 3 LSBs of both offsets must be zero to ensure correct
 684        *   alignment"
 685        *
 686        * We have no guarantee that tile_x and tile_y are correctly aligned,
 687        * since they are determined by the mipmap layout, which is only aligned
 688        * to multiples of 4.
 689        *
 690        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 691        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 692        * up with a better solution.
 693        */
 694       WARN_ONCE((tile_x & 7) || (tile_y & 7),
 695                 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
 696                 "Truncating offset, bad rendering may occur.\n");
 697       tile_x &= ~7;
 698       tile_y &= ~7;
 699
 700       intel_emit_depth_stall_flushes(brw);
 701
 702       BEGIN_BATCH(7);
 703       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 704       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 705                 params->depth_format << 18 |
 706                 1 << 22 | /* hiz enable */
 707                 1 << 28 | /* depth write */
 708                 BRW_SURFACE_2D << 29);
 709       OUT_RELOC(params->depth.mt->region->bo,
 710                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 711                 offset);
 712       OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
 713                 (params->depth.height + tile_y - 1) << 18);
 714       OUT_BATCH(0);
 715       OUT_BATCH(tile_x |
 716                 tile_y << 16);
 717       OUT_BATCH(0);
 718       ADVANCE_BATCH();
 719    }
 720
 721    /* 3DSTATE_HIER_DEPTH_BUFFER */
 722    {
 723       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 724       uint32_t hiz_offset =
 725          intel_region_get_aligned_offset(hiz_region,
 726                                          draw_x & ~tile_mask_x,
 727                                          (draw_y & ~tile_mask_y) / 2, false);
 728
 729       BEGIN_BATCH(3);
 730       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 731       OUT_BATCH(hiz_region->pitch - 1);
 732       OUT_RELOC(hiz_region->bo,
 733                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 734                 hiz_offset);
 735       ADVANCE_BATCH();
 736    }
 737
 738    /* 3DSTATE_STENCIL_BUFFER */
 739    {
 740       BEGIN_BATCH(3);
 741       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 742       OUT_BATCH(0);
 743       OUT_BATCH(0);
 744       ADVANCE_BATCH();
 745    }
 746 }
 747
 748
 749 static void
 750 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 751                               const brw_blorp_params *params)
 752 {
 753    BEGIN_BATCH(7);
 754    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 755    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 756    OUT_BATCH(0);
 757    OUT_BATCH(0);
 758    OUT_BATCH(0);
 759    OUT_BATCH(0);
 760    OUT_BATCH(0);
 761    ADVANCE_BATCH();
 762 }
 763
 764
 765 /* 3DSTATE_CLEAR_PARAMS
 766  *
 767  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 768  * 3DSTATE_CLEAR_PARAMS:
 769  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 770  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 771  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 772  */
 773 static void
 774 gen7_blorp_emit_clear_params(struct brw_context *brw,
 775                              const brw_blorp_params *params)
 776 {
 777    BEGIN_BATCH(3);
 778    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 779    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 780    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 781    ADVANCE_BATCH();
 782 }
 783
 784
 785 /* 3DPRIMITIVE */
 786 static void
 787 gen7_blorp_emit_primitive(struct brw_context *brw,
 788                           const brw_blorp_params *params)
 789 {
 790    BEGIN_BATCH(7);
 791    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 792    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 793              _3DPRIM_RECTLIST);
 794    OUT_BATCH(3); /* vertex count per instance */
 795    OUT_BATCH(0);
 796    OUT_BATCH(1); /* instance count */
 797    OUT_BATCH(0);
 798    OUT_BATCH(0);
 799    ADVANCE_BATCH();
 800 }
 801
 802
 803 /**
 804  * \copydoc gen6_blorp_exec()
 805  */
 806 void
 807 gen7_blorp_exec(struct brw_context *brw,
 808                 const brw_blorp_params *params)
 809 {
 810    brw_blorp_prog_data *prog_data = NULL;
 811    uint32_t cc_blend_state_offset = 0;
 812    uint32_t cc_state_offset = 0;
 813    uint32_t depthstencil_offset;
 814    uint32_t wm_push_const_offset = 0;
 815    uint32_t wm_bind_bo_offset = 0;
 816    uint32_t sampler_offset = 0;
 817
 818    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 819    gen6_blorp_emit_batch_head(brw, params);
 820    gen6_emit_3dstate_multisample(brw, params->num_samples);
 821    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 822    gen6_blorp_emit_state_base_address(brw, params);
 823    gen6_blorp_emit_vertices(brw, params);
 824    gen7_blorp_emit_urb_config(brw, params);
 825    if (params->use_wm_prog) {
 826       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 827       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 828       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 829       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 830    }
 831    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 832    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 833                                                 depthstencil_offset);
 834    if (params->use_wm_prog) {
 835       uint32_t wm_surf_offset_renderbuffer;
 836       uint32_t wm_surf_offset_texture = 0;
 837       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 838       intel_miptree_used_for_rendering(params->dst.mt);
 839       wm_surf_offset_renderbuffer =
 840          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 841                                        I915_GEM_DOMAIN_RENDER,
 842                                        I915_GEM_DOMAIN_RENDER,
 843                                        true /* is_render_target */);
 844       if (params->src.mt) {
 845          wm_surf_offset_texture =
 846             gen7_blorp_emit_surface_state(brw, params, &params->src,
 847                                           I915_GEM_DOMAIN_SAMPLER, 0,
 848                                           false /* is_render_target */);
 849       }
 850       wm_bind_bo_offset =
 851          gen6_blorp_emit_binding_table(brw, params,
 852                                        wm_surf_offset_renderbuffer,
 853                                        wm_surf_offset_texture);
 854       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 855    }
 856    gen7_blorp_emit_vs_disable(brw, params);
 857    gen7_blorp_emit_hs_disable(brw, params);
 858    gen7_blorp_emit_te_disable(brw, params);
 859    gen7_blorp_emit_ds_disable(brw, params);
 860    gen7_blorp_emit_gs_disable(brw, params);
 861    gen7_blorp_emit_streamout_disable(brw, params);
 862    gen6_blorp_emit_clip_disable(brw, params);
 863    gen7_blorp_emit_sf_config(brw, params);
 864    gen7_blorp_emit_wm_config(brw, params, prog_data);
 865    if (params->use_wm_prog) {
 866       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 867                                                 wm_bind_bo_offset);
 868       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 869       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 870    } else {
 871       gen7_blorp_emit_constant_ps_disable(brw, params);
 872    }
 873    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 874    gen7_blorp_emit_cc_viewport(brw, params);
 875
 876    if (params->depth.mt)
 877       gen7_blorp_emit_depth_stencil_config(brw, params);
 878    else
 879       gen7_blorp_emit_depth_disable(brw, params);
 880    gen7_blorp_emit_clear_params(brw, params);
 881    gen6_blorp_emit_drawing_rectangle(brw, params);
 882    gen7_blorp_emit_primitive(brw, params);
 883 }