src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain,
 140                               bool is_render_target)
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    uint32_t wm_surf_offset;
 145    uint32_t width = surface->width;
 146    uint32_t height = surface->height;
 147    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 148     * color surfaces, width and height are measured in pixels; we don't need
 149     * to divide them by 2 as we do for Gen6 (see
 150     * gen6_blorp_emit_surface_state).
 151     */
 152    struct intel_region *region = surface->mt->region;
 153    uint32_t tile_x, tile_y;
 154
 155    uint32_t tiling = surface->map_stencil_as_y_tiled
 156       ? I915_TILING_Y : region->tiling;
 157
 158    uint32_t *surf = (uint32_t *)
 159       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 160    memset(surf, 0, 8 * 4);
 161
 162    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 163              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 164              gen7_surface_tiling_mode(tiling);
 165
 166    if (surface->mt->align_h == 4)
 167       surf[0] |= GEN7_SURFACE_VALIGN_4;
 168    if (surface->mt->align_w == 8)
 169       surf[0] |= GEN7_SURFACE_HALIGN_8;
 170
 171    if (surface->array_spacing_lod0)
 172       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 173    else
 174       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 175
 176    /* reloc */
 177    surf[1] =
 178       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 179
 180    /* Note that the low bits of these fields are missing, so
 181     * there's the possibility of getting in trouble.
 182     */
 183    assert(tile_x % 4 == 0);
 184    assert(tile_y % 2 == 0);
 185    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 186              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 187
 188    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 189              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 190
 191    uint32_t pitch_bytes = region->pitch;
 192    if (surface->map_stencil_as_y_tiled)
 193       pitch_bytes *= 2;
 194    surf[3] = pitch_bytes - 1;
 195
 196    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 197    if (surface->mt->mcs_mt) {
 198       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 199                                 is_render_target);
 200    }
 201
 202    surf[7] = surface->mt->fast_clear_color_value;
 203
 204    if (intel->is_haswell) {
 205       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 206                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 207                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 208                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 209    }
 210
 211    /* Emit relocation to surface contents */
 212    drm_intel_bo_emit_reloc(intel->batch.bo,
 213                            wm_surf_offset + 4,
 214                            region->bo,
 215                            surf[1] - region->bo->offset,
 216                            read_domains, write_domain);
 217
 218    gen7_check_surface_setup(surf, is_render_target);
 219
 220    return wm_surf_offset;
 221 }
 222
 223
 224 /**
 225  * SAMPLER_STATE.  See gen7_update_sampler_state().
 226  */
 227 static uint32_t
 228 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 229                               const brw_blorp_params *params)
 230 {
 231    uint32_t sampler_offset;
 232
 233    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 234       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 235                       sizeof(struct gen7_sampler_state),
 236                       32, &sampler_offset);
 237    memset(sampler, 0, sizeof(*sampler));
 238
 239    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 240    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 241    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 242
 243    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 244    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 245    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 246
 247    //   sampler->ss0.min_mag_neq = 1;
 248
 249    /* Set LOD bias:
 250     */
 251    sampler->ss0.lod_bias = 0;
 252
 253    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 254    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 255
 256    /* Set BaseMipLevel, MaxLOD, MinLOD:
 257     *
 258     * XXX: I don't think that using firstLevel, lastLevel works,
 259     * because we always setup the surface state as if firstLevel ==
 260     * level zero.  Probably have to subtract firstLevel from each of
 261     * these:
 262     */
 263    sampler->ss0.base_level = U_FIXED(0, 1);
 264
 265    sampler->ss1.max_lod = U_FIXED(0, 8);
 266    sampler->ss1.min_lod = U_FIXED(0, 8);
 267
 268    sampler->ss3.non_normalized_coord = 1;
 269
 270    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 271       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 272       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 273    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 274       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 275       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 276
 277    return sampler_offset;
 278 }
 279
 280
 281 /* 3DSTATE_VS
 282  *
 283  * Disable vertex shader.
 284  */
 285 static void
 286 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 287                            const brw_blorp_params *params)
 288 {
 289    struct intel_context *intel = &brw->intel;
 290
 291    BEGIN_BATCH(7);
 292    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 293    OUT_BATCH(0);
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    ADVANCE_BATCH();
 300
 301    BEGIN_BATCH(6);
 302    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 303    OUT_BATCH(0);
 304    OUT_BATCH(0);
 305    OUT_BATCH(0);
 306    OUT_BATCH(0);
 307    OUT_BATCH(0);
 308    ADVANCE_BATCH();
 309 }
 310
 311
 312 /* 3DSTATE_HS
 313  *
 314  * Disable the hull shader.
 315  */
 316 static void
 317 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 318                            const brw_blorp_params *params)
 319 {
 320    struct intel_context *intel = &brw->intel;
 321
 322    BEGIN_BATCH(7);
 323    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    OUT_BATCH(0);
 330    ADVANCE_BATCH();
 331
 332    BEGIN_BATCH(7);
 333    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    OUT_BATCH(0);
 337    OUT_BATCH(0);
 338    OUT_BATCH(0);
 339    OUT_BATCH(0);
 340    ADVANCE_BATCH();
 341 }
 342
 343
 344 /* 3DSTATE_TE
 345  *
 346  * Disable the tesselation engine.
 347  */
 348 static void
 349 gen7_blorp_emit_te_disable(struct brw_context *brw,
 350                            const brw_blorp_params *params)
 351 {
 352    struct intel_context *intel = &brw->intel;
 353
 354    BEGIN_BATCH(4);
 355    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 356    OUT_BATCH(0);
 357    OUT_BATCH(0);
 358    OUT_BATCH(0);
 359    ADVANCE_BATCH();
 360 }
 361
 362
 363 /* 3DSTATE_DS
 364  *
 365  * Disable the domain shader.
 366  */
 367 static void
 368 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 369                            const brw_blorp_params *params)
 370 {
 371    struct intel_context *intel = &brw->intel;
 372
 373    BEGIN_BATCH(7);
 374    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 375    OUT_BATCH(0);
 376    OUT_BATCH(0);
 377    OUT_BATCH(0);
 378    OUT_BATCH(0);
 379    OUT_BATCH(0);
 380    OUT_BATCH(0);
 381    ADVANCE_BATCH();
 382
 383    BEGIN_BATCH(6);
 384    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 385    OUT_BATCH(0);
 386    OUT_BATCH(0);
 387    OUT_BATCH(0);
 388    OUT_BATCH(0);
 389    OUT_BATCH(0);
 390    ADVANCE_BATCH();
 391 }
 392
 393 /* 3DSTATE_GS
 394  *
 395  * Disable the geometry shader.
 396  */
 397 static void
 398 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 399                            const brw_blorp_params *params)
 400 {
 401    struct intel_context *intel = &brw->intel;
 402
 403    BEGIN_BATCH(7);
 404    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 405    OUT_BATCH(0);
 406    OUT_BATCH(0);
 407    OUT_BATCH(0);
 408    OUT_BATCH(0);
 409    OUT_BATCH(0);
 410    OUT_BATCH(0);
 411    ADVANCE_BATCH();
 412
 413    BEGIN_BATCH(7);
 414    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 415    OUT_BATCH(0);
 416    OUT_BATCH(0);
 417    OUT_BATCH(0);
 418    OUT_BATCH(0);
 419    OUT_BATCH(0);
 420    OUT_BATCH(0);
 421    ADVANCE_BATCH();
 422 }
 423
 424 /* 3DSTATE_STREAMOUT
 425  *
 426  * Disable streamout.
 427  */
 428 static void
 429 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 430                                   const brw_blorp_params *params)
 431 {
 432    struct intel_context *intel = &brw->intel;
 433
 434    BEGIN_BATCH(3);
 435    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 436    OUT_BATCH(0);
 437    OUT_BATCH(0);
 438    ADVANCE_BATCH();
 439 }
 440
 441
 442 static void
 443 gen7_blorp_emit_sf_config(struct brw_context *brw,
 444                           const brw_blorp_params *params)
 445 {
 446    struct intel_context *intel = &brw->intel;
 447
 448    /* 3DSTATE_SF
 449     *
 450     * Disable ViewportTransformEnable (dw1.1)
 451     *
 452     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 453     * Primitives Overview":
 454     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 455     *     use of screen- space coordinates).
 456     *
 457     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 458     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 459     *
 460     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 461     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 462     *     SOLID: Any triangle or rectangle object found to be front-facing
 463     *     is rendered as a solid object. This setting is required when
 464     *     (rendering rectangle (RECTLIST) objects.
 465     */
 466    {
 467       BEGIN_BATCH(7);
 468       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 469       OUT_BATCH(params->depth_format <<
 470                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 471       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 472       OUT_BATCH(0);
 473       OUT_BATCH(0);
 474       OUT_BATCH(0);
 475       OUT_BATCH(0);
 476       ADVANCE_BATCH();
 477    }
 478
 479    /* 3DSTATE_SBE */
 480    {
 481       BEGIN_BATCH(14);
 482       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 483       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 484                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 485                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 486       for (int i = 0; i < 12; ++i)
 487          OUT_BATCH(0);
 488       ADVANCE_BATCH();
 489    }
 490 }
 491
 492
 493 /**
 494  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 495  */
 496 static void
 497 gen7_blorp_emit_wm_config(struct brw_context *brw,
 498                           const brw_blorp_params *params,
 499                           brw_blorp_prog_data *prog_data)
 500 {
 501    struct intel_context *intel = &brw->intel;
 502
 503    uint32_t dw1 = 0, dw2 = 0;
 504
 505    switch (params->hiz_op) {
 506    case GEN6_HIZ_OP_DEPTH_CLEAR:
 507       dw1 |= GEN7_WM_DEPTH_CLEAR;
 508       break;
 509    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 510       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 511       break;
 512    case GEN6_HIZ_OP_HIZ_RESOLVE:
 513       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 514       break;
 515    case GEN6_HIZ_OP_NONE:
 516       break;
 517    default:
 518       assert(0);
 519       break;
 520    }
 521    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 522    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 523    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 524    if (params->use_wm_prog) {
 525       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 526       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 527    }
 528
 529       if (params->num_samples > 1) {
 530          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 531          if (prog_data && prog_data->persample_msaa_dispatch)
 532             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 533          else
 534             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 535       } else {
 536          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 537          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 538       }
 539
 540    BEGIN_BATCH(3);
 541    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 542    OUT_BATCH(dw1);
 543    OUT_BATCH(dw2);
 544    ADVANCE_BATCH();
 545 }
 546
 547
 548 /**
 549  * 3DSTATE_PS
 550  *
 551  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 552  * that, thread dispatch info must still be specified.
 553  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 554  *       states that the valid range for this field is [0x3, 0x2f].
 555  *     - A dispatch mode must be given; that is, at least one of the
 556  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 557  *       discovered through simulator error messages.
 558  */
 559 static void
 560 gen7_blorp_emit_ps_config(struct brw_context *brw,
 561                           const brw_blorp_params *params,
 562                           uint32_t prog_offset,
 563                           brw_blorp_prog_data *prog_data)
 564 {
 565    struct intel_context *intel = &brw->intel;
 566    uint32_t dw2, dw4, dw5;
 567    const int max_threads_shift = brw->intel.is_haswell ?
 568       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 569
 570    dw2 = dw4 = dw5 = 0;
 571    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 572
 573    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 574     * what the program is compiled for.  If there isn't, then it shouldn't
 575     * matter because no program is actually being run.  However, the hardware
 576     * gets angry if we don't enable at least one dispatch mode, so just enable
 577     * 16-pixel dispatch unconditionally.
 578     */
 579    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 580
 581    if (intel->is_haswell)
 582       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 583    if (params->use_wm_prog) {
 584       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 585       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 586       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 587    }
 588
 589    switch (params->fast_clear_op) {
 590    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 591       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 592       break;
 593    case GEN7_FAST_CLEAR_OP_RESOLVE:
 594       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 595       break;
 596    default:
 597       break;
 598    }
 599
 600    BEGIN_BATCH(8);
 601    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 602    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 603    OUT_BATCH(dw2);
 604    OUT_BATCH(0);
 605    OUT_BATCH(dw4);
 606    OUT_BATCH(dw5);
 607    OUT_BATCH(0);
 608    OUT_BATCH(0);
 609    ADVANCE_BATCH();
 610 }
 611
 612
 613 static void
 614 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 615                                           const brw_blorp_params *params,
 616                                           uint32_t wm_bind_bo_offset)
 617 {
 618    struct intel_context *intel = &brw->intel;
 619
 620    BEGIN_BATCH(2);
 621    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 622    OUT_BATCH(wm_bind_bo_offset);
 623    ADVANCE_BATCH();
 624 }
 625
 626
 627 static void
 628 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 629                                           const brw_blorp_params *params,
 630                                           uint32_t sampler_offset)
 631 {
 632    struct intel_context *intel = &brw->intel;
 633
 634    BEGIN_BATCH(2);
 635    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 636    OUT_BATCH(sampler_offset);
 637    ADVANCE_BATCH();
 638 }
 639
 640
 641 static void
 642 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 643                             const brw_blorp_params *params,
 644                             uint32_t wm_push_const_offset)
 645 {
 646    struct intel_context *intel = &brw->intel;
 647
 648    /* Make sure the push constants fill an exact integer number of
 649     * registers.
 650     */
 651    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 652
 653    /* There must be at least one register worth of push constant data. */
 654    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 655
 656    /* Enable push constant buffer 0. */
 657    BEGIN_BATCH(7);
 658    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 659              (7 - 2));
 660    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 661    OUT_BATCH(0);
 662    OUT_BATCH(wm_push_const_offset);
 663    OUT_BATCH(0);
 664    OUT_BATCH(0);
 665    OUT_BATCH(0);
 666    ADVANCE_BATCH();
 667 }
 668
 669 static void
 670 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 671                                     const brw_blorp_params *params)
 672 {
 673    struct intel_context *intel = &brw->intel;
 674
 675    BEGIN_BATCH(7);
 676    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 677    OUT_BATCH(0);
 678    OUT_BATCH(0);
 679    OUT_BATCH(0);
 680    OUT_BATCH(0);
 681    OUT_BATCH(0);
 682    OUT_BATCH(0);
 683    ADVANCE_BATCH();
 684 }
 685
 686 static void
 687 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 688                                      const brw_blorp_params *params)
 689 {
 690    struct intel_context *intel = &brw->intel;
 691    struct gl_context *ctx = &intel->ctx;
 692    uint32_t draw_x = params->depth.x_offset;
 693    uint32_t draw_y = params->depth.y_offset;
 694    uint32_t tile_mask_x, tile_mask_y;
 695
 696    brw_get_depthstencil_tile_masks(params->depth.mt,
 697                                    params->depth.level,
 698                                    params->depth.layer,
 699                                    NULL,
 700                                    &tile_mask_x, &tile_mask_y);
 701
 702    /* 3DSTATE_DEPTH_BUFFER */
 703    {
 704       uint32_t tile_x = draw_x & tile_mask_x;
 705       uint32_t tile_y = draw_y & tile_mask_y;
 706       uint32_t offset =
 707          intel_region_get_aligned_offset(params->depth.mt->region,
 708                                          draw_x & ~tile_mask_x,
 709                                          draw_y & ~tile_mask_y, false);
 710
 711       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 712        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 713        * Coordinate Offset X/Y":
 714        *
 715        *   "The 3 LSBs of both offsets must be zero to ensure correct
 716        *   alignment"
 717        *
 718        * We have no guarantee that tile_x and tile_y are correctly aligned,
 719        * since they are determined by the mipmap layout, which is only aligned
 720        * to multiples of 4.
 721        *
 722        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 723        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 724        * up with a better solution.
 725        */
 726       WARN_ONCE((tile_x & 7) || (tile_y & 7),
 727                 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
 728                 "Truncating offset, bad rendering may occur.\n");
 729       tile_x &= ~7;
 730       tile_y &= ~7;
 731
 732       intel_emit_depth_stall_flushes(intel);
 733
 734       BEGIN_BATCH(7);
 735       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 736       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 737                 params->depth_format << 18 |
 738                 1 << 22 | /* hiz enable */
 739                 1 << 28 | /* depth write */
 740                 BRW_SURFACE_2D << 29);
 741       OUT_RELOC(params->depth.mt->region->bo,
 742                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 743                 offset);
 744       OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
 745                 (params->depth.height + tile_y - 1) << 18);
 746       OUT_BATCH(0);
 747       OUT_BATCH(tile_x |
 748                 tile_y << 16);
 749       OUT_BATCH(0);
 750       ADVANCE_BATCH();
 751    }
 752
 753    /* 3DSTATE_HIER_DEPTH_BUFFER */
 754    {
 755       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 756       uint32_t hiz_offset =
 757          intel_region_get_aligned_offset(hiz_region,
 758                                          draw_x & ~tile_mask_x,
 759                                          (draw_y & ~tile_mask_y) / 2, false);
 760
 761       BEGIN_BATCH(3);
 762       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 763       OUT_BATCH(hiz_region->pitch - 1);
 764       OUT_RELOC(hiz_region->bo,
 765                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 766                 hiz_offset);
 767       ADVANCE_BATCH();
 768    }
 769
 770    /* 3DSTATE_STENCIL_BUFFER */
 771    {
 772       BEGIN_BATCH(3);
 773       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 774       OUT_BATCH(0);
 775       OUT_BATCH(0);
 776       ADVANCE_BATCH();
 777    }
 778 }
 779
 780
 781 static void
 782 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 783                               const brw_blorp_params *params)
 784 {
 785    struct intel_context *intel = &brw->intel;
 786
 787    BEGIN_BATCH(7);
 788    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 789    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 790    OUT_BATCH(0);
 791    OUT_BATCH(0);
 792    OUT_BATCH(0);
 793    OUT_BATCH(0);
 794    OUT_BATCH(0);
 795    ADVANCE_BATCH();
 796 }
 797
 798
 799 /* 3DSTATE_CLEAR_PARAMS
 800  *
 801  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 802  * 3DSTATE_CLEAR_PARAMS:
 803  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 804  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 805  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 806  */
 807 static void
 808 gen7_blorp_emit_clear_params(struct brw_context *brw,
 809                              const brw_blorp_params *params)
 810 {
 811    struct intel_context *intel = &brw->intel;
 812
 813    BEGIN_BATCH(3);
 814    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 815    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 816    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 817    ADVANCE_BATCH();
 818 }
 819
 820
 821 /* 3DPRIMITIVE */
 822 static void
 823 gen7_blorp_emit_primitive(struct brw_context *brw,
 824                           const brw_blorp_params *params)
 825 {
 826    struct intel_context *intel = &brw->intel;
 827
 828    BEGIN_BATCH(7);
 829    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 830    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 831              _3DPRIM_RECTLIST);
 832    OUT_BATCH(3); /* vertex count per instance */
 833    OUT_BATCH(0);
 834    OUT_BATCH(1); /* instance count */
 835    OUT_BATCH(0);
 836    OUT_BATCH(0);
 837    ADVANCE_BATCH();
 838 }
 839
 840
 841 /**
 842  * \copydoc gen6_blorp_exec()
 843  */
 844 void
 845 gen7_blorp_exec(struct intel_context *intel,
 846                 const brw_blorp_params *params)
 847 {
 848    struct gl_context *ctx = &intel->ctx;
 849    struct brw_context *brw = brw_context(ctx);
 850    brw_blorp_prog_data *prog_data = NULL;
 851    uint32_t cc_blend_state_offset = 0;
 852    uint32_t cc_state_offset = 0;
 853    uint32_t depthstencil_offset;
 854    uint32_t wm_push_const_offset = 0;
 855    uint32_t wm_bind_bo_offset = 0;
 856    uint32_t sampler_offset = 0;
 857
 858    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 859    gen6_blorp_emit_batch_head(brw, params);
 860    gen6_emit_3dstate_multisample(brw, params->num_samples);
 861    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 862    gen6_blorp_emit_state_base_address(brw, params);
 863    gen6_blorp_emit_vertices(brw, params);
 864    gen7_blorp_emit_urb_config(brw, params);
 865    if (params->use_wm_prog) {
 866       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 867       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 868       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 869       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 870    }
 871    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 872    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 873                                                 depthstencil_offset);
 874    if (params->use_wm_prog) {
 875       uint32_t wm_surf_offset_renderbuffer;
 876       uint32_t wm_surf_offset_texture = 0;
 877       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 878       intel_miptree_used_for_rendering(params->dst.mt);
 879       wm_surf_offset_renderbuffer =
 880          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 881                                        I915_GEM_DOMAIN_RENDER,
 882                                        I915_GEM_DOMAIN_RENDER,
 883                                        true /* is_render_target */);
 884       if (params->src.mt) {
 885          wm_surf_offset_texture =
 886             gen7_blorp_emit_surface_state(brw, params, &params->src,
 887                                           I915_GEM_DOMAIN_SAMPLER, 0,
 888                                           false /* is_render_target */);
 889       }
 890       wm_bind_bo_offset =
 891          gen6_blorp_emit_binding_table(brw, params,
 892                                        wm_surf_offset_renderbuffer,
 893                                        wm_surf_offset_texture);
 894       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 895    }
 896    gen7_blorp_emit_vs_disable(brw, params);
 897    gen7_blorp_emit_hs_disable(brw, params);
 898    gen7_blorp_emit_te_disable(brw, params);
 899    gen7_blorp_emit_ds_disable(brw, params);
 900    gen7_blorp_emit_gs_disable(brw, params);
 901    gen7_blorp_emit_streamout_disable(brw, params);
 902    gen6_blorp_emit_clip_disable(brw, params);
 903    gen7_blorp_emit_sf_config(brw, params);
 904    gen7_blorp_emit_wm_config(brw, params, prog_data);
 905    if (params->use_wm_prog) {
 906       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 907                                                 wm_bind_bo_offset);
 908       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 909       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 910    } else {
 911       gen7_blorp_emit_constant_ps_disable(brw, params);
 912    }
 913    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 914    gen7_blorp_emit_cc_viewport(brw, params);
 915
 916    if (params->depth.mt)
 917       gen7_blorp_emit_depth_stencil_config(brw, params);
 918    else
 919       gen7_blorp_emit_depth_disable(brw, params);
 920    gen7_blorp_emit_clear_params(brw, params);
 921    gen6_blorp_emit_drawing_rectangle(brw, params);
 922    gen7_blorp_emit_primitive(brw, params);
 923 }