src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain,
 140                               bool is_render_target)
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    uint32_t wm_surf_offset;
 145    uint32_t width = surface->width;
 146    uint32_t height = surface->height;
 147    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 148     * color surfaces, width and height are measured in pixels; we don't need
 149     * to divide them by 2 as we do for Gen6 (see
 150     * gen6_blorp_emit_surface_state).
 151     */
 152    struct intel_region *region = surface->mt->region;
 153    uint32_t tile_x, tile_y;
 154
 155    uint32_t tiling = surface->map_stencil_as_y_tiled
 156       ? I915_TILING_Y : region->tiling;
 157
 158    uint32_t *surf = (uint32_t *)
 159       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 160    memset(surf, 0, 8 * 4);
 161
 162    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 163              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 164              gen7_surface_tiling_mode(tiling);
 165
 166    if (surface->mt->align_h == 4)
 167       surf[0] |= GEN7_SURFACE_VALIGN_4;
 168    if (surface->mt->align_w == 8)
 169       surf[0] |= GEN7_SURFACE_HALIGN_8;
 170
 171    if (surface->array_spacing_lod0)
 172       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 173    else
 174       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 175
 176    /* reloc */
 177    surf[1] =
 178       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 179
 180    /* Note that the low bits of these fields are missing, so
 181     * there's the possibility of getting in trouble.
 182     */
 183    assert(tile_x % 4 == 0);
 184    assert(tile_y % 2 == 0);
 185    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 186              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 187
 188    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 189              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 190
 191    uint32_t pitch_bytes = region->pitch;
 192    if (surface->map_stencil_as_y_tiled)
 193       pitch_bytes *= 2;
 194    surf[3] = pitch_bytes - 1;
 195
 196    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 197    if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
 198       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 199                                 is_render_target);
 200    }
 201
 202    if (intel->is_haswell) {
 203       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 204                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 205                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 206                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 207    }
 208
 209    /* Emit relocation to surface contents */
 210    drm_intel_bo_emit_reloc(intel->batch.bo,
 211                            wm_surf_offset + 4,
 212                            region->bo,
 213                            surf[1] - region->bo->offset,
 214                            read_domains, write_domain);
 215
 216    gen7_check_surface_setup(surf, is_render_target);
 217
 218    return wm_surf_offset;
 219 }
 220
 221
 222 /**
 223  * SAMPLER_STATE.  See gen7_update_sampler_state().
 224  */
 225 static uint32_t
 226 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 227                               const brw_blorp_params *params)
 228 {
 229    uint32_t sampler_offset;
 230
 231    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 232       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 233                       sizeof(struct gen7_sampler_state),
 234                       32, &sampler_offset);
 235    memset(sampler, 0, sizeof(*sampler));
 236
 237    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 238    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 239    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 240
 241    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 242    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 243    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 244
 245    //   sampler->ss0.min_mag_neq = 1;
 246
 247    /* Set LOD bias:
 248     */
 249    sampler->ss0.lod_bias = 0;
 250
 251    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 252    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 253
 254    /* Set BaseMipLevel, MaxLOD, MinLOD:
 255     *
 256     * XXX: I don't think that using firstLevel, lastLevel works,
 257     * because we always setup the surface state as if firstLevel ==
 258     * level zero.  Probably have to subtract firstLevel from each of
 259     * these:
 260     */
 261    sampler->ss0.base_level = U_FIXED(0, 1);
 262
 263    sampler->ss1.max_lod = U_FIXED(0, 8);
 264    sampler->ss1.min_lod = U_FIXED(0, 8);
 265
 266    sampler->ss3.non_normalized_coord = 1;
 267
 268    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 269       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 270       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 271    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 272       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 273       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 274
 275    return sampler_offset;
 276 }
 277
 278
 279 /* 3DSTATE_HS
 280  *
 281  * Disable the hull shader.
 282  */
 283 static void
 284 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 285                            const brw_blorp_params *params)
 286 {
 287    struct intel_context *intel = &brw->intel;
 288
 289    BEGIN_BATCH(7);
 290    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 291    OUT_BATCH(0);
 292    OUT_BATCH(0);
 293    OUT_BATCH(0);
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    ADVANCE_BATCH();
 298 }
 299
 300
 301 /* 3DSTATE_TE
 302  *
 303  * Disable the tesselation engine.
 304  */
 305 static void
 306 gen7_blorp_emit_te_disable(struct brw_context *brw,
 307                            const brw_blorp_params *params)
 308 {
 309    struct intel_context *intel = &brw->intel;
 310
 311    BEGIN_BATCH(4);
 312    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    ADVANCE_BATCH();
 317 }
 318
 319
 320 /* 3DSTATE_DS
 321  *
 322  * Disable the domain shader.
 323  */
 324 static void
 325 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 326                            const brw_blorp_params *params)
 327 {
 328    struct intel_context *intel = &brw->intel;
 329
 330    BEGIN_BATCH(6);
 331    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 332    OUT_BATCH(0);
 333    OUT_BATCH(0);
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    OUT_BATCH(0);
 337    ADVANCE_BATCH();
 338 }
 339
 340
 341 /* 3DSTATE_STREAMOUT
 342  *
 343  * Disable streamout.
 344  */
 345 static void
 346 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 347                                   const brw_blorp_params *params)
 348 {
 349    struct intel_context *intel = &brw->intel;
 350
 351    BEGIN_BATCH(3);
 352    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 353    OUT_BATCH(0);
 354    OUT_BATCH(0);
 355    ADVANCE_BATCH();
 356 }
 357
 358
 359 static void
 360 gen7_blorp_emit_sf_config(struct brw_context *brw,
 361                           const brw_blorp_params *params)
 362 {
 363    struct intel_context *intel = &brw->intel;
 364
 365    /* 3DSTATE_SF
 366     *
 367     * Disable ViewportTransformEnable (dw1.1)
 368     *
 369     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 370     * Primitives Overview":
 371     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 372     *     use of screen- space coordinates).
 373     *
 374     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 375     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 376     *
 377     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 378     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 379     *     SOLID: Any triangle or rectangle object found to be front-facing
 380     *     is rendered as a solid object. This setting is required when
 381     *     (rendering rectangle (RECTLIST) objects.
 382     */
 383    {
 384       BEGIN_BATCH(7);
 385       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 386       OUT_BATCH(params->depth_format <<
 387                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 388       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 389       OUT_BATCH(0);
 390       OUT_BATCH(0);
 391       OUT_BATCH(0);
 392       OUT_BATCH(0);
 393       ADVANCE_BATCH();
 394    }
 395
 396    /* 3DSTATE_SBE */
 397    {
 398       BEGIN_BATCH(14);
 399       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 400       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 401                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 402                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 403       for (int i = 0; i < 12; ++i)
 404          OUT_BATCH(0);
 405       ADVANCE_BATCH();
 406    }
 407 }
 408
 409
 410 /**
 411  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 412  */
 413 static void
 414 gen7_blorp_emit_wm_config(struct brw_context *brw,
 415                           const brw_blorp_params *params,
 416                           brw_blorp_prog_data *prog_data)
 417 {
 418    struct intel_context *intel = &brw->intel;
 419
 420    uint32_t dw1 = 0, dw2 = 0;
 421
 422    switch (params->hiz_op) {
 423    case GEN6_HIZ_OP_DEPTH_CLEAR:
 424       dw1 |= GEN7_WM_DEPTH_CLEAR;
 425       break;
 426    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 427       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 428       break;
 429    case GEN6_HIZ_OP_HIZ_RESOLVE:
 430       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 431       break;
 432    case GEN6_HIZ_OP_NONE:
 433       break;
 434    default:
 435       assert(0);
 436       break;
 437    }
 438    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 439    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 440    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 441    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 442    if (params->use_wm_prog) {
 443       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 444       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 445    }
 446
 447       if (params->num_samples > 1) {
 448          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 449          if (prog_data && prog_data->persample_msaa_dispatch)
 450             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 451          else
 452             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 453       } else {
 454          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 455          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 456       }
 457
 458    BEGIN_BATCH(3);
 459    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 460    OUT_BATCH(dw1);
 461    OUT_BATCH(dw2);
 462    ADVANCE_BATCH();
 463 }
 464
 465
 466 /**
 467  * 3DSTATE_PS
 468  *
 469  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 470  * that, thread dispatch info must still be specified.
 471  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 472  *       states that the valid range for this field is [0x3, 0x2f].
 473  *     - A dispatch mode must be given; that is, at least one of the
 474  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 475  *       discovered through simulator error messages.
 476  */
 477 static void
 478 gen7_blorp_emit_ps_config(struct brw_context *brw,
 479                           const brw_blorp_params *params,
 480                           uint32_t prog_offset,
 481                           brw_blorp_prog_data *prog_data)
 482 {
 483    struct intel_context *intel = &brw->intel;
 484    uint32_t dw2, dw4, dw5;
 485    const int max_threads_shift = brw->intel.is_haswell ?
 486       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 487
 488    dw2 = dw4 = dw5 = 0;
 489    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 490
 491    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 492     * what the program is compiled for.  If there isn't, then it shouldn't
 493     * matter because no program is actually being run.  However, the hardware
 494     * gets angry if we don't enable at least one dispatch mode, so just enable
 495     * 16-pixel dispatch unconditionally.
 496     */
 497    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 498
 499    if (intel->is_haswell)
 500       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 501    if (params->use_wm_prog) {
 502       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 503       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 504       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 505    }
 506
 507    BEGIN_BATCH(8);
 508    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 509    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 510    OUT_BATCH(dw2);
 511    OUT_BATCH(0);
 512    OUT_BATCH(dw4);
 513    OUT_BATCH(dw5);
 514    OUT_BATCH(0);
 515    OUT_BATCH(0);
 516    ADVANCE_BATCH();
 517 }
 518
 519
 520 static void
 521 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 522                                           const brw_blorp_params *params,
 523                                           uint32_t wm_bind_bo_offset)
 524 {
 525    struct intel_context *intel = &brw->intel;
 526
 527    BEGIN_BATCH(2);
 528    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 529    OUT_BATCH(wm_bind_bo_offset);
 530    ADVANCE_BATCH();
 531 }
 532
 533
 534 static void
 535 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 536                                           const brw_blorp_params *params,
 537                                           uint32_t sampler_offset)
 538 {
 539    struct intel_context *intel = &brw->intel;
 540
 541    BEGIN_BATCH(2);
 542    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 543    OUT_BATCH(sampler_offset);
 544    ADVANCE_BATCH();
 545 }
 546
 547
 548 static void
 549 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 550                             const brw_blorp_params *params,
 551                             uint32_t wm_push_const_offset)
 552 {
 553    struct intel_context *intel = &brw->intel;
 554
 555    /* Make sure the push constants fill an exact integer number of
 556     * registers.
 557     */
 558    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 559
 560    /* There must be at least one register worth of push constant data. */
 561    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 562
 563    /* Enable push constant buffer 0. */
 564    BEGIN_BATCH(7);
 565    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 566              (7 - 2));
 567    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 568    OUT_BATCH(0);
 569    OUT_BATCH(wm_push_const_offset);
 570    OUT_BATCH(0);
 571    OUT_BATCH(0);
 572    OUT_BATCH(0);
 573    ADVANCE_BATCH();
 574 }
 575
 576
 577 static void
 578 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 579                                      const brw_blorp_params *params)
 580 {
 581    struct intel_context *intel = &brw->intel;
 582    struct gl_context *ctx = &intel->ctx;
 583    uint32_t draw_x = params->depth.x_offset;
 584    uint32_t draw_y = params->depth.y_offset;
 585    uint32_t tile_mask_x, tile_mask_y;
 586
 587    brw_get_depthstencil_tile_masks(params->depth.mt,
 588                                    params->depth.level,
 589                                    params->depth.layer,
 590                                    NULL,
 591                                    &tile_mask_x, &tile_mask_y);
 592
 593    /* 3DSTATE_DEPTH_BUFFER */
 594    {
 595       uint32_t tile_x = draw_x & tile_mask_x;
 596       uint32_t tile_y = draw_y & tile_mask_y;
 597       uint32_t offset =
 598          intel_region_get_aligned_offset(params->depth.mt->region,
 599                                          draw_x & ~tile_mask_x,
 600                                          draw_y & ~tile_mask_y, false);
 601
 602       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 603        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 604        * Coordinate Offset X/Y":
 605        *
 606        *   "The 3 LSBs of both offsets must be zero to ensure correct
 607        *   alignment"
 608        *
 609        * We have no guarantee that tile_x and tile_y are correctly aligned,
 610        * since they are determined by the mipmap layout, which is only aligned
 611        * to multiples of 4.
 612        *
 613        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 614        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 615        * up with a better solution.
 616        */
 617       WARN_ONCE((tile_x & 7) || (tile_y & 7),
 618                 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
 619                 "Truncating offset, bad rendering may occur.\n");
 620       tile_x &= ~7;
 621       tile_y &= ~7;
 622
 623       intel_emit_depth_stall_flushes(intel);
 624
 625       BEGIN_BATCH(7);
 626       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 627       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 628                 params->depth_format << 18 |
 629                 1 << 22 | /* hiz enable */
 630                 1 << 28 | /* depth write */
 631                 BRW_SURFACE_2D << 29);
 632       OUT_RELOC(params->depth.mt->region->bo,
 633                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 634                 offset);
 635       OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
 636                 (params->depth.height + tile_y - 1) << 18);
 637       OUT_BATCH(0);
 638       OUT_BATCH(tile_x |
 639                 tile_y << 16);
 640       OUT_BATCH(0);
 641       ADVANCE_BATCH();
 642    }
 643
 644    /* 3DSTATE_HIER_DEPTH_BUFFER */
 645    {
 646       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 647       uint32_t hiz_offset =
 648          intel_region_get_aligned_offset(hiz_region,
 649                                          draw_x & ~tile_mask_x,
 650                                          (draw_y & ~tile_mask_y) / 2, false);
 651
 652       BEGIN_BATCH(3);
 653       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 654       OUT_BATCH(hiz_region->pitch - 1);
 655       OUT_RELOC(hiz_region->bo,
 656                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 657                 hiz_offset);
 658       ADVANCE_BATCH();
 659    }
 660
 661    /* 3DSTATE_STENCIL_BUFFER */
 662    {
 663       BEGIN_BATCH(3);
 664       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 665       OUT_BATCH(0);
 666       OUT_BATCH(0);
 667       ADVANCE_BATCH();
 668    }
 669 }
 670
 671
 672 static void
 673 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 674                               const brw_blorp_params *params)
 675 {
 676    struct intel_context *intel = &brw->intel;
 677
 678    BEGIN_BATCH(7);
 679    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 680    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 681    OUT_BATCH(0);
 682    OUT_BATCH(0);
 683    OUT_BATCH(0);
 684    OUT_BATCH(0);
 685    OUT_BATCH(0);
 686    ADVANCE_BATCH();
 687 }
 688
 689
 690 /* 3DSTATE_CLEAR_PARAMS
 691  *
 692  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 693  * 3DSTATE_CLEAR_PARAMS:
 694  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 695  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 696  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 697  */
 698 static void
 699 gen7_blorp_emit_clear_params(struct brw_context *brw,
 700                              const brw_blorp_params *params)
 701 {
 702    struct intel_context *intel = &brw->intel;
 703
 704    BEGIN_BATCH(3);
 705    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 706    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 707    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 708    ADVANCE_BATCH();
 709 }
 710
 711
 712 /* 3DPRIMITIVE */
 713 static void
 714 gen7_blorp_emit_primitive(struct brw_context *brw,
 715                           const brw_blorp_params *params)
 716 {
 717    struct intel_context *intel = &brw->intel;
 718
 719    BEGIN_BATCH(7);
 720    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 721    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 722              _3DPRIM_RECTLIST);
 723    OUT_BATCH(3); /* vertex count per instance */
 724    OUT_BATCH(0);
 725    OUT_BATCH(1); /* instance count */
 726    OUT_BATCH(0);
 727    OUT_BATCH(0);
 728    ADVANCE_BATCH();
 729 }
 730
 731
 732 /**
 733  * \copydoc gen6_blorp_exec()
 734  */
 735 void
 736 gen7_blorp_exec(struct intel_context *intel,
 737                 const brw_blorp_params *params)
 738 {
 739    struct gl_context *ctx = &intel->ctx;
 740    struct brw_context *brw = brw_context(ctx);
 741    brw_blorp_prog_data *prog_data = NULL;
 742    uint32_t cc_blend_state_offset = 0;
 743    uint32_t cc_state_offset = 0;
 744    uint32_t depthstencil_offset;
 745    uint32_t wm_push_const_offset = 0;
 746    uint32_t wm_bind_bo_offset = 0;
 747    uint32_t sampler_offset = 0;
 748
 749    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 750    gen6_blorp_emit_batch_head(brw, params);
 751    gen7_allocate_push_constants(brw);
 752    gen6_emit_3dstate_multisample(brw, params->num_samples);
 753    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 754    gen6_blorp_emit_state_base_address(brw, params);
 755    gen6_blorp_emit_vertices(brw, params);
 756    gen7_blorp_emit_urb_config(brw, params);
 757    if (params->use_wm_prog) {
 758       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 759       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 760       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 761       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 762    }
 763    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 764    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 765                                                 depthstencil_offset);
 766    if (params->use_wm_prog) {
 767       uint32_t wm_surf_offset_renderbuffer;
 768       uint32_t wm_surf_offset_texture;
 769       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 770       wm_surf_offset_renderbuffer =
 771          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 772                                        I915_GEM_DOMAIN_RENDER,
 773                                        I915_GEM_DOMAIN_RENDER,
 774                                        true /* is_render_target */);
 775       wm_surf_offset_texture =
 776          gen7_blorp_emit_surface_state(brw, params, &params->src,
 777                                        I915_GEM_DOMAIN_SAMPLER, 0,
 778                                        false /* is_render_target */);
 779       wm_bind_bo_offset =
 780          gen6_blorp_emit_binding_table(brw, params,
 781                                        wm_surf_offset_renderbuffer,
 782                                        wm_surf_offset_texture);
 783       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 784    }
 785    gen6_blorp_emit_vs_disable(brw, params);
 786    gen7_blorp_emit_hs_disable(brw, params);
 787    gen7_blorp_emit_te_disable(brw, params);
 788    gen7_blorp_emit_ds_disable(brw, params);
 789    gen6_blorp_emit_gs_disable(brw, params);
 790    gen7_blorp_emit_streamout_disable(brw, params);
 791    gen6_blorp_emit_clip_disable(brw, params);
 792    gen7_blorp_emit_sf_config(brw, params);
 793    gen7_blorp_emit_wm_config(brw, params, prog_data);
 794    if (params->use_wm_prog) {
 795       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 796                                                 wm_bind_bo_offset);
 797       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 798       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 799    }
 800    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 801    gen7_blorp_emit_cc_viewport(brw, params);
 802
 803    if (params->depth.mt)
 804       gen7_blorp_emit_depth_stencil_config(brw, params);
 805    else
 806       gen7_blorp_emit_depth_disable(brw, params);
 807    gen7_blorp_emit_clear_params(brw, params);
 808    gen6_blorp_emit_drawing_rectangle(brw, params);
 809    gen7_blorp_emit_primitive(brw, params);
 810
 811    /* See comments above at first invocation of intel_flush() in
 812     * gen6_blorp_emit_batch_head().
 813     */
 814    intel_flush(ctx);
 815
 816    /* Be safe. */
 817    brw->state.dirty.brw = ~0;
 818    brw->state.dirty.cache = ~0;
 819 }