src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain)
 140 {
 141    struct intel_context *intel = &brw->intel;
 142
 143    uint32_t wm_surf_offset;
 144    uint32_t width, height;
 145    surface->get_miplevel_dims(&width, &height);
 146    if (surface->num_samples > 0) { /* TODO: wrong for 8x */
 147       width /= 2;
 148       height /= 2;
 149    }
 150    if (surface->map_stencil_as_y_tiled) {
 151       width *= 2;
 152       height /= 2;
 153    }
 154    struct intel_region *region = surface->mt->region;
 155
 156    /* TODO: handle other formats */
 157    uint32_t format = surface->map_stencil_as_y_tiled
 158       ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 159
 160    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 161       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 162                       &wm_surf_offset);
 163    memset(surf, 0, sizeof(*surf));
 164
 165    if (surface->mt->align_h == 4)
 166       surf->ss0.vertical_alignment = 1;
 167    if (surface->mt->align_w == 8)
 168       surf->ss0.horizontal_alignment = 1;
 169
 170    surf->ss0.surface_format = format;
 171    surf->ss0.surface_type = BRW_SURFACE_2D;
 172    surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
 173       GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
 174
 175    /* reloc */
 176    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 177
 178    surf->ss2.width = width - 1;
 179    surf->ss2.height = height - 1;
 180
 181    uint32_t tiling = surface->map_stencil_as_y_tiled
 182       ? I915_TILING_Y : region->tiling;
 183    gen7_set_surface_tiling(surf, tiling);
 184
 185    uint32_t pitch_bytes = region->pitch * region->cpp;
 186    if (surface->map_stencil_as_y_tiled)
 187       pitch_bytes *= 2;
 188    surf->ss3.pitch = pitch_bytes - 1;
 189
 190    gen7_set_surface_num_multisamples(surf, surface->num_samples);
 191
 192    if (intel->is_haswell) {
 193       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 194       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 195       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 196       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 197    }
 198
 199    /* Emit relocation to surface contents */
 200    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 201                            wm_surf_offset +
 202                            offsetof(struct gen7_surface_state, ss1),
 203                            region->bo,
 204                            surf->ss1.base_addr - region->bo->offset,
 205                            read_domains, write_domain);
 206
 207    return wm_surf_offset;
 208 }
 209
 210
 211 /**
 212  * SAMPLER_STATE.  See gen7_update_sampler_state().
 213  */
 214 static uint32_t
 215 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 216                               const brw_blorp_params *params)
 217 {
 218    uint32_t sampler_offset;
 219
 220    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 221       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 222                       sizeof(struct gen7_sampler_state),
 223                       32, &sampler_offset);
 224    memset(sampler, 0, sizeof(*sampler));
 225
 226    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 227    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 228    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 229
 230    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 231    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 232    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 233
 234    //   sampler->ss0.min_mag_neq = 1;
 235
 236    /* Set LOD bias:
 237     */
 238    sampler->ss0.lod_bias = 0;
 239
 240    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 241    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 242
 243    /* Set BaseMipLevel, MaxLOD, MinLOD:
 244     *
 245     * XXX: I don't think that using firstLevel, lastLevel works,
 246     * because we always setup the surface state as if firstLevel ==
 247     * level zero.  Probably have to subtract firstLevel from each of
 248     * these:
 249     */
 250    sampler->ss0.base_level = U_FIXED(0, 1);
 251
 252    sampler->ss1.max_lod = U_FIXED(0, 8);
 253    sampler->ss1.min_lod = U_FIXED(0, 8);
 254
 255    sampler->ss3.non_normalized_coord = 1;
 256
 257    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 258       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 259       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 260    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 261       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 262       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 263
 264    return sampler_offset;
 265 }
 266
 267
 268 /* 3DSTATE_HS
 269  *
 270  * Disable the hull shader.
 271  */
 272 static void
 273 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 274                            const brw_blorp_params *params)
 275 {
 276    struct intel_context *intel = &brw->intel;
 277
 278    BEGIN_BATCH(7);
 279    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 280    OUT_BATCH(0);
 281    OUT_BATCH(0);
 282    OUT_BATCH(0);
 283    OUT_BATCH(0);
 284    OUT_BATCH(0);
 285    OUT_BATCH(0);
 286    ADVANCE_BATCH();
 287 }
 288
 289
 290 /* 3DSTATE_TE
 291  *
 292  * Disable the tesselation engine.
 293  */
 294 static void
 295 gen7_blorp_emit_te_disable(struct brw_context *brw,
 296                            const brw_blorp_params *params)
 297 {
 298    struct intel_context *intel = &brw->intel;
 299
 300    BEGIN_BATCH(4);
 301    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 302    OUT_BATCH(0);
 303    OUT_BATCH(0);
 304    OUT_BATCH(0);
 305    ADVANCE_BATCH();
 306 }
 307
 308
 309 /* 3DSTATE_DS
 310  *
 311  * Disable the domain shader.
 312  */
 313 static void
 314 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 315                            const brw_blorp_params *params)
 316 {
 317    struct intel_context *intel = &brw->intel;
 318
 319    BEGIN_BATCH(6);
 320    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 321    OUT_BATCH(0);
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    ADVANCE_BATCH();
 327 }
 328
 329
 330 /* 3DSTATE_STREAMOUT
 331  *
 332  * Disable streamout.
 333  */
 334 static void
 335 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 336                                   const brw_blorp_params *params)
 337 {
 338    struct intel_context *intel = &brw->intel;
 339
 340    BEGIN_BATCH(3);
 341    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 342    OUT_BATCH(0);
 343    OUT_BATCH(0);
 344    ADVANCE_BATCH();
 345 }
 346
 347
 348 static void
 349 gen7_blorp_emit_sf_config(struct brw_context *brw,
 350                           const brw_blorp_params *params)
 351 {
 352    struct intel_context *intel = &brw->intel;
 353
 354    /* 3DSTATE_SF
 355     *
 356     * Disable ViewportTransformEnable (dw1.1)
 357     *
 358     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 359     * Primitives Overview":
 360     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 361     *     use of screen- space coordinates).
 362     *
 363     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 364     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 365     *
 366     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 367     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 368     *     SOLID: Any triangle or rectangle object found to be front-facing
 369     *     is rendered as a solid object. This setting is required when
 370     *     (rendering rectangle (RECTLIST) objects.
 371     */
 372    {
 373       BEGIN_BATCH(7);
 374       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 375       OUT_BATCH(params->depth_format <<
 376                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 377       OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 378       OUT_BATCH(0);
 379       OUT_BATCH(0);
 380       OUT_BATCH(0);
 381       OUT_BATCH(0);
 382       ADVANCE_BATCH();
 383    }
 384
 385    /* 3DSTATE_SBE */
 386    {
 387       BEGIN_BATCH(14);
 388       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 389       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 390                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 391                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 392       for (int i = 0; i < 12; ++i)
 393          OUT_BATCH(0);
 394       ADVANCE_BATCH();
 395    }
 396 }
 397
 398
 399 /**
 400  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 401  */
 402 static void
 403 gen7_blorp_emit_wm_config(struct brw_context *brw,
 404                           const brw_blorp_params *params,
 405                           brw_blorp_prog_data *prog_data)
 406 {
 407    struct intel_context *intel = &brw->intel;
 408
 409    uint32_t dw1 = 0, dw2 = 0;
 410
 411    switch (params->hiz_op) {
 412    case GEN6_HIZ_OP_DEPTH_CLEAR:
 413       dw1 |= GEN7_WM_DEPTH_CLEAR;
 414       break;
 415    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 416       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 417       break;
 418    case GEN6_HIZ_OP_HIZ_RESOLVE:
 419       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 420       break;
 421    case GEN6_HIZ_OP_NONE:
 422       break;
 423    default:
 424       assert(0);
 425       break;
 426    }
 427    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 428    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 429    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 430    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 431    if (params->use_wm_prog) {
 432       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 433       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 434    }
 435
 436       if (params->num_samples > 0) {
 437          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 438          if (prog_data && prog_data->persample_msaa_dispatch)
 439             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 440          else
 441             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 442       } else {
 443          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 444          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 445       }
 446
 447    BEGIN_BATCH(3);
 448    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 449    OUT_BATCH(dw1);
 450    OUT_BATCH(dw2);
 451    ADVANCE_BATCH();
 452 }
 453
 454
 455 /**
 456  * 3DSTATE_PS
 457  *
 458  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 459  * that, thread dispatch info must still be specified.
 460  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 461  *       states that the valid range for this field is [0x3, 0x2f].
 462  *     - A dispatch mode must be given; that is, at least one of the
 463  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 464  *       discovered through simulator error messages.
 465  */
 466 static void
 467 gen7_blorp_emit_ps_config(struct brw_context *brw,
 468                           const brw_blorp_params *params,
 469                           uint32_t prog_offset,
 470                           brw_blorp_prog_data *prog_data)
 471 {
 472    struct intel_context *intel = &brw->intel;
 473    uint32_t dw2, dw4, dw5;
 474    const int max_threads_shift = brw->intel.is_haswell ?
 475       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 476
 477    dw2 = dw4 = dw5 = 0;
 478    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 479
 480    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 481     * what the program is compiled for.  If there isn't, then it shouldn't
 482     * matter because no program is actually being run.  However, the hardware
 483     * gets angry if we don't enable at least one dispatch mode, so just enable
 484     * 16-pixel dispatch unconditionally.
 485     */
 486    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 487
 488    if (intel->is_haswell)
 489       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 490    if (params->use_wm_prog) {
 491       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 492       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 493       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 494    }
 495
 496    BEGIN_BATCH(8);
 497    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 498    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 499    OUT_BATCH(dw2);
 500    OUT_BATCH(0);
 501    OUT_BATCH(dw4);
 502    OUT_BATCH(dw5);
 503    OUT_BATCH(0);
 504    OUT_BATCH(0);
 505    ADVANCE_BATCH();
 506 }
 507
 508
 509 static void
 510 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 511                                           const brw_blorp_params *params,
 512                                           uint32_t wm_bind_bo_offset)
 513 {
 514    struct intel_context *intel = &brw->intel;
 515
 516    BEGIN_BATCH(2);
 517    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 518    OUT_BATCH(wm_bind_bo_offset);
 519    ADVANCE_BATCH();
 520 }
 521
 522
 523 static void
 524 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 525                                           const brw_blorp_params *params,
 526                                           uint32_t sampler_offset)
 527 {
 528    struct intel_context *intel = &brw->intel;
 529
 530    BEGIN_BATCH(2);
 531    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 532    OUT_BATCH(sampler_offset);
 533    ADVANCE_BATCH();
 534 }
 535
 536
 537 static void
 538 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 539                             const brw_blorp_params *params,
 540                             uint32_t wm_push_const_offset)
 541 {
 542    struct intel_context *intel = &brw->intel;
 543
 544    /* Make sure the push constants fill an exact integer number of
 545     * registers.
 546     */
 547    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 548
 549    /* There must be at least one register worth of push constant data. */
 550    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 551
 552    /* Enable push constant buffer 0. */
 553    BEGIN_BATCH(7);
 554    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 555              (7 - 2));
 556    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 557    OUT_BATCH(0);
 558    OUT_BATCH(wm_push_const_offset);
 559    OUT_BATCH(0);
 560    OUT_BATCH(0);
 561    OUT_BATCH(0);
 562    ADVANCE_BATCH();
 563 }
 564
 565
 566 static void
 567 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 568                                      const brw_blorp_params *params)
 569 {
 570    struct intel_context *intel = &brw->intel;
 571    uint32_t draw_x, draw_y;
 572    uint32_t tile_mask_x, tile_mask_y;
 573
 574    if (params->depth.mt) {
 575       params->depth.get_draw_offsets(&draw_x, &draw_y);
 576       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 577    }
 578
 579    /* 3DSTATE_DEPTH_BUFFER */
 580    {
 581       uint32_t width, height;
 582       params->depth.get_miplevel_dims(&width, &height);
 583
 584       uint32_t tile_x = draw_x & tile_mask_x;
 585       uint32_t tile_y = draw_y & tile_mask_y;
 586       uint32_t offset =
 587          intel_region_get_aligned_offset(params->depth.mt->region,
 588                                          draw_x & ~tile_mask_x,
 589                                          draw_y & ~tile_mask_y);
 590
 591       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 592        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 593        * Coordinate Offset X/Y":
 594        *
 595        *   "The 3 LSBs of both offsets must be zero to ensure correct
 596        *   alignment"
 597        *
 598        * We have no guarantee that tile_x and tile_y are correctly aligned,
 599        * since they are determined by the mipmap layout, which is only aligned
 600        * to multiples of 4.
 601        *
 602        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 603        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 604        * up with a better solution.
 605        */
 606       tile_x &= ~7;
 607       tile_y &= ~7;
 608
 609       intel_emit_depth_stall_flushes(intel);
 610
 611       BEGIN_BATCH(7);
 612       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 613       uint32_t pitch_bytes =
 614          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 615       OUT_BATCH((pitch_bytes - 1) |
 616                 params->depth_format << 18 |
 617                 1 << 22 | /* hiz enable */
 618                 1 << 28 | /* depth write */
 619                 BRW_SURFACE_2D << 29);
 620       OUT_RELOC(params->depth.mt->region->bo,
 621                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 622                 offset);
 623       OUT_BATCH((width + tile_x - 1) << 4 |
 624                 (height + tile_y - 1) << 18);
 625       OUT_BATCH(0);
 626       OUT_BATCH(tile_x |
 627                 tile_y << 16);
 628       OUT_BATCH(0);
 629       ADVANCE_BATCH();
 630    }
 631
 632    /* 3DSTATE_HIER_DEPTH_BUFFER */
 633    {
 634       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 635       uint32_t hiz_offset =
 636          intel_region_get_aligned_offset(hiz_region,
 637                                          draw_x & ~tile_mask_x,
 638                                          (draw_y & ~tile_mask_y) / 2);
 639
 640       BEGIN_BATCH(3);
 641       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 642       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 643       OUT_RELOC(hiz_region->bo,
 644                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 645                 hiz_offset);
 646       ADVANCE_BATCH();
 647    }
 648
 649    /* 3DSTATE_STENCIL_BUFFER */
 650    {
 651       BEGIN_BATCH(3);
 652       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 653       OUT_BATCH(0);
 654       OUT_BATCH(0);
 655       ADVANCE_BATCH();
 656    }
 657 }
 658
 659
 660 static void
 661 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 662                               const brw_blorp_params *params)
 663 {
 664    struct intel_context *intel = &brw->intel;
 665
 666    BEGIN_BATCH(7);
 667    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 668    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 669    OUT_BATCH(0);
 670    OUT_BATCH(0);
 671    OUT_BATCH(0);
 672    OUT_BATCH(0);
 673    OUT_BATCH(0);
 674    ADVANCE_BATCH();
 675 }
 676
 677
 678 /* 3DSTATE_CLEAR_PARAMS
 679  *
 680  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 681  * 3DSTATE_CLEAR_PARAMS:
 682  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 683  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 684  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 685  */
 686 static void
 687 gen7_blorp_emit_clear_params(struct brw_context *brw,
 688                              const brw_blorp_params *params)
 689 {
 690    struct intel_context *intel = &brw->intel;
 691
 692    BEGIN_BATCH(3);
 693    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 694    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 695    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 696    ADVANCE_BATCH();
 697 }
 698
 699
 700 /* 3DPRIMITIVE */
 701 static void
 702 gen7_blorp_emit_primitive(struct brw_context *brw,
 703                           const brw_blorp_params *params)
 704 {
 705    struct intel_context *intel = &brw->intel;
 706
 707    BEGIN_BATCH(7);
 708    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 709    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 710              _3DPRIM_RECTLIST);
 711    OUT_BATCH(3); /* vertex count per instance */
 712    OUT_BATCH(0);
 713    OUT_BATCH(1); /* instance count */
 714    OUT_BATCH(0);
 715    OUT_BATCH(0);
 716    ADVANCE_BATCH();
 717 }
 718
 719
 720 /**
 721  * \copydoc gen6_blorp_exec()
 722  */
 723 void
 724 gen7_blorp_exec(struct intel_context *intel,
 725                 const brw_blorp_params *params)
 726 {
 727    struct gl_context *ctx = &intel->ctx;
 728    struct brw_context *brw = brw_context(ctx);
 729    brw_blorp_prog_data *prog_data = NULL;
 730    uint32_t cc_blend_state_offset = 0;
 731    uint32_t cc_state_offset = 0;
 732    uint32_t depthstencil_offset;
 733    uint32_t wm_push_const_offset = 0;
 734    uint32_t wm_bind_bo_offset = 0;
 735    uint32_t sampler_offset = 0;
 736
 737    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 738    gen6_blorp_emit_batch_head(brw, params);
 739    gen7_allocate_push_constants(brw);
 740    gen6_emit_3dstate_multisample(brw, params->num_samples);
 741    gen6_emit_3dstate_sample_mask(brw, params->num_samples);
 742    gen6_blorp_emit_state_base_address(brw, params);
 743    gen6_blorp_emit_vertices(brw, params);
 744    gen7_blorp_emit_urb_config(brw, params);
 745    if (params->use_wm_prog) {
 746       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 747       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 748       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 749       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 750    }
 751    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 752    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 753                                                 depthstencil_offset);
 754    if (params->use_wm_prog) {
 755       uint32_t wm_surf_offset_renderbuffer;
 756       uint32_t wm_surf_offset_texture;
 757       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 758       wm_surf_offset_renderbuffer =
 759          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 760                                        I915_GEM_DOMAIN_RENDER,
 761                                        I915_GEM_DOMAIN_RENDER);
 762       wm_surf_offset_texture =
 763          gen7_blorp_emit_surface_state(brw, params, &params->src,
 764                                        I915_GEM_DOMAIN_SAMPLER, 0);
 765       wm_bind_bo_offset =
 766          gen6_blorp_emit_binding_table(brw, params,
 767                                        wm_surf_offset_renderbuffer,
 768                                        wm_surf_offset_texture);
 769       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 770    }
 771    gen6_blorp_emit_vs_disable(brw, params);
 772    gen7_blorp_emit_hs_disable(brw, params);
 773    gen7_blorp_emit_te_disable(brw, params);
 774    gen7_blorp_emit_ds_disable(brw, params);
 775    gen6_blorp_emit_gs_disable(brw, params);
 776    gen7_blorp_emit_streamout_disable(brw, params);
 777    gen6_blorp_emit_clip_disable(brw, params);
 778    gen7_blorp_emit_sf_config(brw, params);
 779    gen7_blorp_emit_wm_config(brw, params, prog_data);
 780    if (params->use_wm_prog) {
 781       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 782                                                 wm_bind_bo_offset);
 783       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 784       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 785    }
 786    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 787    gen7_blorp_emit_cc_viewport(brw, params);
 788
 789    if (params->depth.mt)
 790       gen7_blorp_emit_depth_stencil_config(brw, params);
 791    else
 792       gen7_blorp_emit_depth_disable(brw, params);
 793    gen7_blorp_emit_clear_params(brw, params);
 794    gen6_blorp_emit_drawing_rectangle(brw, params);
 795    gen7_blorp_emit_primitive(brw, params);
 796
 797    /* See comments above at first invocation of intel_flush() in
 798     * gen6_blorp_emit_batch_head().
 799     */
 800    intel_flush(ctx);
 801
 802    /* Be safe. */
 803    brw->state.dirty.brw = ~0;
 804    brw->state.dirty.cache = ~0;
 805 }