2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen7_blorp.h"
43 * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
44 * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
45 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
46 * programmed in order for the programming of this state to be
50 gen7_blorp_emit_urb_config(struct brw_context
*brw
,
51 const brw_blorp_params
*params
)
53 /* The minimum valid value is 32. See 3DSTATE_URB_VS,
54 * Dword 1.15:0 "VS Number of URB Entries".
56 int num_vs_entries
= 32;
58 int vs_start
= 2; /* skip over push constants */
60 gen7_emit_urb_state(brw
, num_vs_entries
, vs_size
, vs_start
);
64 /* 3DSTATE_BLEND_STATE_POINTERS */
66 gen7_blorp_emit_blend_state_pointer(struct brw_context
*brw
,
67 const brw_blorp_params
*params
,
68 uint32_t cc_blend_state_offset
)
70 struct intel_context
*intel
= &brw
->intel
;
73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS
<< 16 | (2 - 2));
74 OUT_BATCH(cc_blend_state_offset
| 1);
79 /* 3DSTATE_CC_STATE_POINTERS */
81 gen7_blorp_emit_cc_state_pointer(struct brw_context
*brw
,
82 const brw_blorp_params
*params
,
83 uint32_t cc_state_offset
)
85 struct intel_context
*intel
= &brw
->intel
;
88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
89 OUT_BATCH(cc_state_offset
| 1);
94 gen7_blorp_emit_cc_viewport(struct brw_context
*brw
,
95 const brw_blorp_params
*params
)
97 struct intel_context
*intel
= &brw
->intel
;
98 struct brw_cc_viewport
*ccv
;
99 uint32_t cc_vp_offset
;
101 ccv
= (struct brw_cc_viewport
*)brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
104 ccv
->min_depth
= 0.0;
105 ccv
->max_depth
= 1.0;
108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC
<< 16 | (2 - 2));
109 OUT_BATCH(cc_vp_offset
);
114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context
*brw
,
120 const brw_blorp_params
*params
,
121 uint32_t depthstencil_offset
)
123 struct intel_context
*intel
= &brw
->intel
;
126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
<< 16 | (2 - 2));
127 OUT_BATCH(depthstencil_offset
| 1);
132 /* SURFACE_STATE for renderbuffer or texture surface (see
133 * brw_update_renderbuffer_surface and brw_update_texture_surface)
136 gen7_blorp_emit_surface_state(struct brw_context
*brw
,
137 const brw_blorp_params
*params
,
138 const brw_blorp_surface_info
*surface
,
139 uint32_t read_domains
, uint32_t write_domain
,
140 bool is_render_target
)
142 struct intel_context
*intel
= &brw
->intel
;
144 uint32_t wm_surf_offset
;
145 uint32_t width
= surface
->width
;
146 uint32_t height
= surface
->height
;
147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
148 * color surfaces, width and height are measured in pixels; we don't need
149 * to divide them by 2 as we do for Gen6 (see
150 * gen6_blorp_emit_surface_state).
152 struct intel_region
*region
= surface
->mt
->region
;
153 uint32_t tile_x
, tile_y
;
155 uint32_t tiling
= surface
->map_stencil_as_y_tiled
156 ? I915_TILING_Y
: region
->tiling
;
158 uint32_t *surf
= (uint32_t *)
159 brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32, &wm_surf_offset
);
160 memset(surf
, 0, 8 * 4);
162 surf
[0] = BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
163 surface
->brw_surfaceformat
<< BRW_SURFACE_FORMAT_SHIFT
|
164 gen7_surface_tiling_mode(tiling
);
166 if (surface
->mt
->align_h
== 4)
167 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
168 if (surface
->mt
->align_w
== 8)
169 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
171 if (surface
->array_spacing_lod0
)
172 surf
[0] |= GEN7_SURFACE_ARYSPC_LOD0
;
174 surf
[0] |= GEN7_SURFACE_ARYSPC_FULL
;
178 surface
->compute_tile_offsets(&tile_x
, &tile_y
) + region
->bo
->offset
;
180 /* Note that the low bits of these fields are missing, so
181 * there's the possibility of getting in trouble.
183 assert(tile_x
% 4 == 0);
184 assert(tile_y
% 2 == 0);
185 surf
[5] = SET_FIELD(tile_x
/ 4, BRW_SURFACE_X_OFFSET
) |
186 SET_FIELD(tile_y
/ 2, BRW_SURFACE_Y_OFFSET
);
188 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
189 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
191 uint32_t pitch_bytes
= region
->pitch
;
192 if (surface
->map_stencil_as_y_tiled
)
194 surf
[3] = pitch_bytes
- 1;
196 surf
[4] = gen7_surface_msaa_bits(surface
->num_samples
, surface
->msaa_layout
);
197 if (surface
->mt
->mcs_mt
) {
198 gen7_set_surface_mcs_info(brw
, surf
, wm_surf_offset
, surface
->mt
->mcs_mt
,
202 if (intel
->is_haswell
) {
203 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
204 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
205 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
206 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
209 /* Emit relocation to surface contents */
210 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
213 surf
[1] - region
->bo
->offset
,
214 read_domains
, write_domain
);
216 gen7_check_surface_setup(surf
, is_render_target
);
218 return wm_surf_offset
;
223 * SAMPLER_STATE. See gen7_update_sampler_state().
226 gen7_blorp_emit_sampler_state(struct brw_context
*brw
,
227 const brw_blorp_params
*params
)
229 uint32_t sampler_offset
;
231 struct gen7_sampler_state
*sampler
= (struct gen7_sampler_state
*)
232 brw_state_batch(brw
, AUB_TRACE_SAMPLER_STATE
,
233 sizeof(struct gen7_sampler_state
),
234 32, &sampler_offset
);
235 memset(sampler
, 0, sizeof(*sampler
));
237 sampler
->ss0
.min_filter
= BRW_MAPFILTER_LINEAR
;
238 sampler
->ss0
.mip_filter
= BRW_MIPFILTER_NONE
;
239 sampler
->ss0
.mag_filter
= BRW_MAPFILTER_LINEAR
;
241 sampler
->ss3
.r_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
242 sampler
->ss3
.s_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
243 sampler
->ss3
.t_wrap_mode
= BRW_TEXCOORDMODE_CLAMP
;
245 // sampler->ss0.min_mag_neq = 1;
249 sampler
->ss0
.lod_bias
= 0;
251 sampler
->ss0
.lod_preclamp
= 1; /* OpenGL mode */
252 sampler
->ss0
.default_color_mode
= 0; /* OpenGL/DX10 mode */
254 /* Set BaseMipLevel, MaxLOD, MinLOD:
256 * XXX: I don't think that using firstLevel, lastLevel works,
257 * because we always setup the surface state as if firstLevel ==
258 * level zero. Probably have to subtract firstLevel from each of
261 sampler
->ss0
.base_level
= U_FIXED(0, 1);
263 sampler
->ss1
.max_lod
= U_FIXED(0, 8);
264 sampler
->ss1
.min_lod
= U_FIXED(0, 8);
266 sampler
->ss3
.non_normalized_coord
= 1;
268 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN
|
269 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN
|
270 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN
;
271 sampler
->ss3
.address_round
|= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG
|
272 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG
|
273 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG
;
275 return sampler_offset
;
281 * Disable vertex shader.
284 gen7_blorp_emit_vs_disable(struct brw_context
*brw
,
285 const brw_blorp_params
*params
)
287 struct intel_context
*intel
= &brw
->intel
;
290 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (7 - 2));
300 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
312 * Disable the hull shader.
315 gen7_blorp_emit_hs_disable(struct brw_context
*brw
,
316 const brw_blorp_params
*params
)
318 struct intel_context
*intel
= &brw
->intel
;
321 OUT_BATCH(_3DSTATE_CONSTANT_HS
<< 16 | (7 - 2));
331 OUT_BATCH(_3DSTATE_HS
<< 16 | (7 - 2));
344 * Disable the tesselation engine.
347 gen7_blorp_emit_te_disable(struct brw_context
*brw
,
348 const brw_blorp_params
*params
)
350 struct intel_context
*intel
= &brw
->intel
;
353 OUT_BATCH(_3DSTATE_TE
<< 16 | (4 - 2));
363 * Disable the domain shader.
366 gen7_blorp_emit_ds_disable(struct brw_context
*brw
,
367 const brw_blorp_params
*params
)
369 struct intel_context
*intel
= &brw
->intel
;
372 OUT_BATCH(_3DSTATE_CONSTANT_DS
<< 16 | (7 - 2));
382 OUT_BATCH(_3DSTATE_DS
<< 16 | (6 - 2));
393 * Disable the geometry shader.
396 gen7_blorp_emit_gs_disable(struct brw_context
*brw
,
397 const brw_blorp_params
*params
)
399 struct intel_context
*intel
= &brw
->intel
;
402 OUT_BATCH(_3DSTATE_CONSTANT_GS
<< 16 | (7 - 2));
412 OUT_BATCH(_3DSTATE_GS
<< 16 | (7 - 2));
427 gen7_blorp_emit_streamout_disable(struct brw_context
*brw
,
428 const brw_blorp_params
*params
)
430 struct intel_context
*intel
= &brw
->intel
;
433 OUT_BATCH(_3DSTATE_STREAMOUT
<< 16 | (3 - 2));
441 gen7_blorp_emit_sf_config(struct brw_context
*brw
,
442 const brw_blorp_params
*params
)
444 struct intel_context
*intel
= &brw
->intel
;
448 * Disable ViewportTransformEnable (dw1.1)
450 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
451 * Primitives Overview":
452 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
453 * use of screen- space coordinates).
455 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
456 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
458 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
459 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
460 * SOLID: Any triangle or rectangle object found to be front-facing
461 * is rendered as a solid object. This setting is required when
462 * (rendering rectangle (RECTLIST) objects.
466 OUT_BATCH(_3DSTATE_SF
<< 16 | (7 - 2));
467 OUT_BATCH(params
->depth_format
<<
468 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT
);
469 OUT_BATCH(params
->num_samples
> 1 ? GEN6_SF_MSRAST_ON_PATTERN
: 0);
480 OUT_BATCH(_3DSTATE_SBE
<< 16 | (14 - 2));
481 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT
| /* only position */
482 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT
|
483 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT
);
484 for (int i
= 0; i
< 12; ++i
)
492 * Disable thread dispatch (dw5.19) and enable the HiZ op.
495 gen7_blorp_emit_wm_config(struct brw_context
*brw
,
496 const brw_blorp_params
*params
,
497 brw_blorp_prog_data
*prog_data
)
499 struct intel_context
*intel
= &brw
->intel
;
501 uint32_t dw1
= 0, dw2
= 0;
503 switch (params
->hiz_op
) {
504 case GEN6_HIZ_OP_DEPTH_CLEAR
:
505 dw1
|= GEN7_WM_DEPTH_CLEAR
;
507 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
508 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
510 case GEN6_HIZ_OP_HIZ_RESOLVE
:
511 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
513 case GEN6_HIZ_OP_NONE
:
519 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
520 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
521 dw1
|= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
; /* No interp */
522 if (params
->use_wm_prog
) {
523 dw1
|= GEN7_WM_KILL_ENABLE
; /* TODO: temporarily smash on */
524 dw1
|= GEN7_WM_DISPATCH_ENABLE
; /* We are rendering */
527 if (params
->num_samples
> 1) {
528 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
529 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
530 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
532 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
534 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
535 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
539 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
549 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
550 * that, thread dispatch info must still be specified.
551 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
552 * states that the valid range for this field is [0x3, 0x2f].
553 * - A dispatch mode must be given; that is, at least one of the
554 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
555 * discovered through simulator error messages.
558 gen7_blorp_emit_ps_config(struct brw_context
*brw
,
559 const brw_blorp_params
*params
,
560 uint32_t prog_offset
,
561 brw_blorp_prog_data
*prog_data
)
563 struct intel_context
*intel
= &brw
->intel
;
564 uint32_t dw2
, dw4
, dw5
;
565 const int max_threads_shift
= brw
->intel
.is_haswell
?
566 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
569 dw4
|= (brw
->max_wm_threads
- 1) << max_threads_shift
;
571 /* If there's a WM program, we need to do 16-pixel dispatch since that's
572 * what the program is compiled for. If there isn't, then it shouldn't
573 * matter because no program is actually being run. However, the hardware
574 * gets angry if we don't enable at least one dispatch mode, so just enable
575 * 16-pixel dispatch unconditionally.
577 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
579 if (intel
->is_haswell
)
580 dw4
|= SET_FIELD(1, HSW_PS_SAMPLE_MASK
); /* 1 sample for now */
581 if (params
->use_wm_prog
) {
582 dw2
|= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT
; /* Up to 4 samplers */
583 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
584 dw5
|= prog_data
->first_curbe_grf
<< GEN7_PS_DISPATCH_START_GRF_SHIFT_0
;
588 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
589 OUT_BATCH(params
->use_wm_prog
? prog_offset
: 0);
601 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context
*brw
,
602 const brw_blorp_params
*params
,
603 uint32_t wm_bind_bo_offset
)
605 struct intel_context
*intel
= &brw
->intel
;
608 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS
<< 16 | (2 - 2));
609 OUT_BATCH(wm_bind_bo_offset
);
615 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context
*brw
,
616 const brw_blorp_params
*params
,
617 uint32_t sampler_offset
)
619 struct intel_context
*intel
= &brw
->intel
;
622 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
623 OUT_BATCH(sampler_offset
);
629 gen7_blorp_emit_constant_ps(struct brw_context
*brw
,
630 const brw_blorp_params
*params
,
631 uint32_t wm_push_const_offset
)
633 struct intel_context
*intel
= &brw
->intel
;
635 /* Make sure the push constants fill an exact integer number of
638 assert(sizeof(brw_blorp_wm_push_constants
) % 32 == 0);
640 /* There must be at least one register worth of push constant data. */
641 assert(BRW_BLORP_NUM_PUSH_CONST_REGS
> 0);
643 /* Enable push constant buffer 0. */
645 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 |
647 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS
);
649 OUT_BATCH(wm_push_const_offset
);
657 gen7_blorp_emit_constant_ps_disable(struct brw_context
*brw
,
658 const brw_blorp_params
*params
)
660 struct intel_context
*intel
= &brw
->intel
;
663 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (7 - 2));
674 gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw
,
675 const brw_blorp_params
*params
)
677 struct intel_context
*intel
= &brw
->intel
;
678 struct gl_context
*ctx
= &intel
->ctx
;
679 uint32_t draw_x
= params
->depth
.x_offset
;
680 uint32_t draw_y
= params
->depth
.y_offset
;
681 uint32_t tile_mask_x
, tile_mask_y
;
683 brw_get_depthstencil_tile_masks(params
->depth
.mt
,
687 &tile_mask_x
, &tile_mask_y
);
689 /* 3DSTATE_DEPTH_BUFFER */
691 uint32_t tile_x
= draw_x
& tile_mask_x
;
692 uint32_t tile_y
= draw_y
& tile_mask_y
;
694 intel_region_get_aligned_offset(params
->depth
.mt
->region
,
695 draw_x
& ~tile_mask_x
,
696 draw_y
& ~tile_mask_y
, false);
698 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
699 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
700 * Coordinate Offset X/Y":
702 * "The 3 LSBs of both offsets must be zero to ensure correct
705 * We have no guarantee that tile_x and tile_y are correctly aligned,
706 * since they are determined by the mipmap layout, which is only aligned
709 * So, to avoid hanging the GPU, just smash the low order 3 bits of
710 * tile_x and tile_y to 0. This is a temporary workaround until we come
711 * up with a better solution.
713 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
714 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
715 "Truncating offset, bad rendering may occur.\n");
719 intel_emit_depth_stall_flushes(intel
);
722 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
723 OUT_BATCH((params
->depth
.mt
->region
->pitch
- 1) |
724 params
->depth_format
<< 18 |
725 1 << 22 | /* hiz enable */
726 1 << 28 | /* depth write */
727 BRW_SURFACE_2D
<< 29);
728 OUT_RELOC(params
->depth
.mt
->region
->bo
,
729 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
731 OUT_BATCH((params
->depth
.width
+ tile_x
- 1) << 4 |
732 (params
->depth
.height
+ tile_y
- 1) << 18);
740 /* 3DSTATE_HIER_DEPTH_BUFFER */
742 struct intel_region
*hiz_region
= params
->depth
.mt
->hiz_mt
->region
;
743 uint32_t hiz_offset
=
744 intel_region_get_aligned_offset(hiz_region
,
745 draw_x
& ~tile_mask_x
,
746 (draw_y
& ~tile_mask_y
) / 2, false);
749 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
750 OUT_BATCH(hiz_region
->pitch
- 1);
751 OUT_RELOC(hiz_region
->bo
,
752 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
757 /* 3DSTATE_STENCIL_BUFFER */
760 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
769 gen7_blorp_emit_depth_disable(struct brw_context
*brw
,
770 const brw_blorp_params
*params
)
772 struct intel_context
*intel
= &brw
->intel
;
775 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
776 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT
<< 18 | (BRW_SURFACE_NULL
<< 29));
786 /* 3DSTATE_CLEAR_PARAMS
788 * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
789 * 3DSTATE_CLEAR_PARAMS:
790 * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
791 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
792 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
795 gen7_blorp_emit_clear_params(struct brw_context
*brw
,
796 const brw_blorp_params
*params
)
798 struct intel_context
*intel
= &brw
->intel
;
801 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
802 OUT_BATCH(params
->depth
.mt
? params
->depth
.mt
->depth_clear_value
: 0);
803 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID
);
810 gen7_blorp_emit_primitive(struct brw_context
*brw
,
811 const brw_blorp_params
*params
)
813 struct intel_context
*intel
= &brw
->intel
;
816 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
817 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
|
819 OUT_BATCH(3); /* vertex count per instance */
821 OUT_BATCH(1); /* instance count */
829 * \copydoc gen6_blorp_exec()
832 gen7_blorp_exec(struct intel_context
*intel
,
833 const brw_blorp_params
*params
)
835 struct gl_context
*ctx
= &intel
->ctx
;
836 struct brw_context
*brw
= brw_context(ctx
);
837 brw_blorp_prog_data
*prog_data
= NULL
;
838 uint32_t cc_blend_state_offset
= 0;
839 uint32_t cc_state_offset
= 0;
840 uint32_t depthstencil_offset
;
841 uint32_t wm_push_const_offset
= 0;
842 uint32_t wm_bind_bo_offset
= 0;
843 uint32_t sampler_offset
= 0;
845 uint32_t prog_offset
= params
->get_wm_prog(brw
, &prog_data
);
846 gen6_blorp_emit_batch_head(brw
, params
);
847 gen6_emit_3dstate_multisample(brw
, params
->num_samples
);
848 gen6_emit_3dstate_sample_mask(brw
, params
->num_samples
, 1.0, false, ~0u);
849 gen6_blorp_emit_state_base_address(brw
, params
);
850 gen6_blorp_emit_vertices(brw
, params
);
851 gen7_blorp_emit_urb_config(brw
, params
);
852 if (params
->use_wm_prog
) {
853 cc_blend_state_offset
= gen6_blorp_emit_blend_state(brw
, params
);
854 cc_state_offset
= gen6_blorp_emit_cc_state(brw
, params
);
855 gen7_blorp_emit_blend_state_pointer(brw
, params
, cc_blend_state_offset
);
856 gen7_blorp_emit_cc_state_pointer(brw
, params
, cc_state_offset
);
858 depthstencil_offset
= gen6_blorp_emit_depth_stencil_state(brw
, params
);
859 gen7_blorp_emit_depth_stencil_state_pointers(brw
, params
,
860 depthstencil_offset
);
861 if (params
->use_wm_prog
) {
862 uint32_t wm_surf_offset_renderbuffer
;
863 uint32_t wm_surf_offset_texture
= 0;
864 wm_push_const_offset
= gen6_blorp_emit_wm_constants(brw
, params
);
865 intel_miptree_used_for_rendering(params
->dst
.mt
);
866 wm_surf_offset_renderbuffer
=
867 gen7_blorp_emit_surface_state(brw
, params
, ¶ms
->dst
,
868 I915_GEM_DOMAIN_RENDER
,
869 I915_GEM_DOMAIN_RENDER
,
870 true /* is_render_target */);
871 if (params
->src
.mt
) {
872 wm_surf_offset_texture
=
873 gen7_blorp_emit_surface_state(brw
, params
, ¶ms
->src
,
874 I915_GEM_DOMAIN_SAMPLER
, 0,
875 false /* is_render_target */);
878 gen6_blorp_emit_binding_table(brw
, params
,
879 wm_surf_offset_renderbuffer
,
880 wm_surf_offset_texture
);
881 sampler_offset
= gen7_blorp_emit_sampler_state(brw
, params
);
883 gen7_blorp_emit_vs_disable(brw
, params
);
884 gen7_blorp_emit_hs_disable(brw
, params
);
885 gen7_blorp_emit_te_disable(brw
, params
);
886 gen7_blorp_emit_ds_disable(brw
, params
);
887 gen7_blorp_emit_gs_disable(brw
, params
);
888 gen7_blorp_emit_streamout_disable(brw
, params
);
889 gen6_blorp_emit_clip_disable(brw
, params
);
890 gen7_blorp_emit_sf_config(brw
, params
);
891 gen7_blorp_emit_wm_config(brw
, params
, prog_data
);
892 if (params
->use_wm_prog
) {
893 gen7_blorp_emit_binding_table_pointers_ps(brw
, params
,
895 gen7_blorp_emit_sampler_state_pointers_ps(brw
, params
, sampler_offset
);
896 gen7_blorp_emit_constant_ps(brw
, params
, wm_push_const_offset
);
898 gen7_blorp_emit_constant_ps_disable(brw
, params
);
900 gen7_blorp_emit_ps_config(brw
, params
, prog_offset
, prog_data
);
901 gen7_blorp_emit_cc_viewport(brw
, params
);
903 if (params
->depth
.mt
)
904 gen7_blorp_emit_depth_stencil_config(brw
, params
);
906 gen7_blorp_emit_depth_disable(brw
, params
);
907 gen7_blorp_emit_clear_params(brw
, params
);
908 gen6_blorp_emit_drawing_rectangle(brw
, params
);
909 gen7_blorp_emit_primitive(brw
, params
);