src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  44  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  45  *
  46  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  47  *     programmed in order for the programming of this state to be
  48  *     valid.
  49  */
  50 static void
  51 gen7_blorp_emit_urb_config(struct brw_context *brw,
  52                            const brw_blorp_params *params)
  53 {
  54    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  55     * Dword 1.15:0 "VS Number of URB Entries".
  56     */
  57    int num_vs_entries = 32;
  58    int vs_size = 2;
  59    int vs_start = 2; /* skip over push constants */
  60
  61    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  62 }
  63
  64
  65 /* 3DSTATE_BLEND_STATE_POINTERS */
  66 static void
  67 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  68                                     const brw_blorp_params *params,
  69                                     uint32_t cc_blend_state_offset)
  70 {
  71    BEGIN_BATCH(2);
  72    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  73    OUT_BATCH(cc_blend_state_offset | 1);
  74    ADVANCE_BATCH();
  75 }
  76
  77
  78 /* 3DSTATE_CC_STATE_POINTERS */
  79 static void
  80 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  81                                  const brw_blorp_params *params,
  82                                  uint32_t cc_state_offset)
  83 {
  84    BEGIN_BATCH(2);
  85    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  86    OUT_BATCH(cc_state_offset | 1);
  87    ADVANCE_BATCH();
  88 }
  89
  90 static void
  91 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  92                             const brw_blorp_params *params)
  93 {
  94    struct brw_cc_viewport *ccv;
  95    uint32_t cc_vp_offset;
  96
  97    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
  98                                                    sizeof(*ccv), 32,
  99                                                    &cc_vp_offset);
 100    ccv->min_depth = 0.0;
 101    ccv->max_depth = 1.0;
 102
 103    BEGIN_BATCH(2);
 104    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 105    OUT_BATCH(cc_vp_offset);
 106    ADVANCE_BATCH();
 107 }
 108
 109
 110 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 111  *
 112  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 113  */
 114 static void
 115 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 116                                              const brw_blorp_params *params,
 117                                              uint32_t depthstencil_offset)
 118 {
 119    BEGIN_BATCH(2);
 120    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 121    OUT_BATCH(depthstencil_offset | 1);
 122    ADVANCE_BATCH();
 123 }
 124
 125
 126 /* SURFACE_STATE for renderbuffer or texture surface (see
 127  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 128  */
 129 static uint32_t
 130 gen7_blorp_emit_surface_state(struct brw_context *brw,
 131                               const brw_blorp_params *params,
 132                               const brw_blorp_surface_info *surface,
 133                               uint32_t read_domains, uint32_t write_domain,
 134                               bool is_render_target)
 135 {
 136    uint32_t wm_surf_offset;
 137    uint32_t width = surface->width;
 138    uint32_t height = surface->height;
 139    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 140     * color surfaces, width and height are measured in pixels; we don't need
 141     * to divide them by 2 as we do for Gen6 (see
 142     * gen6_blorp_emit_surface_state).
 143     */
 144    struct intel_region *region = surface->mt->region;
 145    uint32_t tile_x, tile_y;
 146
 147    uint32_t tiling = surface->map_stencil_as_y_tiled
 148       ? I915_TILING_Y : region->tiling;
 149
 150    uint32_t *surf = (uint32_t *)
 151       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 152    memset(surf, 0, 8 * 4);
 153
 154    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 155              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 156              gen7_surface_tiling_mode(tiling);
 157
 158    if (surface->mt->align_h == 4)
 159       surf[0] |= GEN7_SURFACE_VALIGN_4;
 160    if (surface->mt->align_w == 8)
 161       surf[0] |= GEN7_SURFACE_HALIGN_8;
 162
 163    if (surface->array_spacing_lod0)
 164       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 165    else
 166       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 167
 168    /* reloc */
 169    surf[1] =
 170       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 171
 172    /* Note that the low bits of these fields are missing, so
 173     * there's the possibility of getting in trouble.
 174     */
 175    assert(tile_x % 4 == 0);
 176    assert(tile_y % 2 == 0);
 177    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 178              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 179
 180    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 181              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 182
 183    uint32_t pitch_bytes = region->pitch;
 184    if (surface->map_stencil_as_y_tiled)
 185       pitch_bytes *= 2;
 186    surf[3] = pitch_bytes - 1;
 187
 188    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 189    if (surface->mt->mcs_mt) {
 190       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 191                                 is_render_target);
 192    }
 193
 194    surf[7] = surface->mt->fast_clear_color_value;
 195
 196    if (brw->is_haswell) {
 197       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 198                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 199                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 200                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 201    }
 202
 203    /* Emit relocation to surface contents */
 204    drm_intel_bo_emit_reloc(brw->batch.bo,
 205                            wm_surf_offset + 4,
 206                            region->bo,
 207                            surf[1] - region->bo->offset,
 208                            read_domains, write_domain);
 209
 210    gen7_check_surface_setup(surf, is_render_target);
 211
 212    return wm_surf_offset;
 213 }
 214
 215
 216 /**
 217  * SAMPLER_STATE.  See gen7_update_sampler_state().
 218  */
 219 static uint32_t
 220 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 221                               const brw_blorp_params *params)
 222 {
 223    uint32_t sampler_offset;
 224
 225    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 226       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 227                       sizeof(struct gen7_sampler_state),
 228                       32, &sampler_offset);
 229    memset(sampler, 0, sizeof(*sampler));
 230
 231    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 232    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 233    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 234
 235    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 236    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 237    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 238
 239    //   sampler->ss0.min_mag_neq = 1;
 240
 241    /* Set LOD bias:
 242     */
 243    sampler->ss0.lod_bias = 0;
 244
 245    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 246    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 247
 248    /* Set BaseMipLevel, MaxLOD, MinLOD:
 249     *
 250     * XXX: I don't think that using firstLevel, lastLevel works,
 251     * because we always setup the surface state as if firstLevel ==
 252     * level zero.  Probably have to subtract firstLevel from each of
 253     * these:
 254     */
 255    sampler->ss0.base_level = U_FIXED(0, 1);
 256
 257    sampler->ss1.max_lod = U_FIXED(0, 8);
 258    sampler->ss1.min_lod = U_FIXED(0, 8);
 259
 260    sampler->ss3.non_normalized_coord = 1;
 261
 262    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 263       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 264       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 265    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 266       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 267       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 268
 269    return sampler_offset;
 270 }
 271
 272
 273 /* 3DSTATE_VS
 274  *
 275  * Disable vertex shader.
 276  */
 277 static void
 278 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 279                            const brw_blorp_params *params)
 280 {
 281    BEGIN_BATCH(7);
 282    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 283    OUT_BATCH(0);
 284    OUT_BATCH(0);
 285    OUT_BATCH(0);
 286    OUT_BATCH(0);
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    ADVANCE_BATCH();
 290
 291    BEGIN_BATCH(6);
 292    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 293    OUT_BATCH(0);
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    ADVANCE_BATCH();
 299 }
 300
 301
 302 /* 3DSTATE_HS
 303  *
 304  * Disable the hull shader.
 305  */
 306 static void
 307 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 308                            const brw_blorp_params *params)
 309 {
 310    BEGIN_BATCH(7);
 311    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 312    OUT_BATCH(0);
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    ADVANCE_BATCH();
 319
 320    BEGIN_BATCH(7);
 321    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    ADVANCE_BATCH();
 329 }
 330
 331
 332 /* 3DSTATE_TE
 333  *
 334  * Disable the tesselation engine.
 335  */
 336 static void
 337 gen7_blorp_emit_te_disable(struct brw_context *brw,
 338                            const brw_blorp_params *params)
 339 {
 340    BEGIN_BATCH(4);
 341    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 342    OUT_BATCH(0);
 343    OUT_BATCH(0);
 344    OUT_BATCH(0);
 345    ADVANCE_BATCH();
 346 }
 347
 348
 349 /* 3DSTATE_DS
 350  *
 351  * Disable the domain shader.
 352  */
 353 static void
 354 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 355                            const brw_blorp_params *params)
 356 {
 357    BEGIN_BATCH(7);
 358    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 359    OUT_BATCH(0);
 360    OUT_BATCH(0);
 361    OUT_BATCH(0);
 362    OUT_BATCH(0);
 363    OUT_BATCH(0);
 364    OUT_BATCH(0);
 365    ADVANCE_BATCH();
 366
 367    BEGIN_BATCH(6);
 368    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 369    OUT_BATCH(0);
 370    OUT_BATCH(0);
 371    OUT_BATCH(0);
 372    OUT_BATCH(0);
 373    OUT_BATCH(0);
 374    ADVANCE_BATCH();
 375 }
 376
 377 /* 3DSTATE_GS
 378  *
 379  * Disable the geometry shader.
 380  */
 381 static void
 382 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 383                            const brw_blorp_params *params)
 384 {
 385    BEGIN_BATCH(7);
 386    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 387    OUT_BATCH(0);
 388    OUT_BATCH(0);
 389    OUT_BATCH(0);
 390    OUT_BATCH(0);
 391    OUT_BATCH(0);
 392    OUT_BATCH(0);
 393    ADVANCE_BATCH();
 394
 395    BEGIN_BATCH(7);
 396    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 397    OUT_BATCH(0);
 398    OUT_BATCH(0);
 399    OUT_BATCH(0);
 400    OUT_BATCH(0);
 401    OUT_BATCH(0);
 402    OUT_BATCH(0);
 403    ADVANCE_BATCH();
 404 }
 405
 406 /* 3DSTATE_STREAMOUT
 407  *
 408  * Disable streamout.
 409  */
 410 static void
 411 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 412                                   const brw_blorp_params *params)
 413 {
 414    BEGIN_BATCH(3);
 415    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 416    OUT_BATCH(0);
 417    OUT_BATCH(0);
 418    ADVANCE_BATCH();
 419 }
 420
 421
 422 static void
 423 gen7_blorp_emit_sf_config(struct brw_context *brw,
 424                           const brw_blorp_params *params)
 425 {
 426    /* 3DSTATE_SF
 427     *
 428     * Disable ViewportTransformEnable (dw1.1)
 429     *
 430     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 431     * Primitives Overview":
 432     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 433     *     use of screen- space coordinates).
 434     *
 435     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 436     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 437     *
 438     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 439     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 440     *     SOLID: Any triangle or rectangle object found to be front-facing
 441     *     is rendered as a solid object. This setting is required when
 442     *     (rendering rectangle (RECTLIST) objects.
 443     */
 444    {
 445       BEGIN_BATCH(7);
 446       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 447       OUT_BATCH(params->depth_format <<
 448                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 449       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 450       OUT_BATCH(0);
 451       OUT_BATCH(0);
 452       OUT_BATCH(0);
 453       OUT_BATCH(0);
 454       ADVANCE_BATCH();
 455    }
 456
 457    /* 3DSTATE_SBE */
 458    {
 459       BEGIN_BATCH(14);
 460       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 461       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 462                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 463                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 464       for (int i = 0; i < 12; ++i)
 465          OUT_BATCH(0);
 466       ADVANCE_BATCH();
 467    }
 468 }
 469
 470
 471 /**
 472  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 473  */
 474 static void
 475 gen7_blorp_emit_wm_config(struct brw_context *brw,
 476                           const brw_blorp_params *params,
 477                           brw_blorp_prog_data *prog_data)
 478 {
 479    uint32_t dw1 = 0, dw2 = 0;
 480
 481    switch (params->hiz_op) {
 482    case GEN6_HIZ_OP_DEPTH_CLEAR:
 483       dw1 |= GEN7_WM_DEPTH_CLEAR;
 484       break;
 485    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 486       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 487       break;
 488    case GEN6_HIZ_OP_HIZ_RESOLVE:
 489       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 490       break;
 491    case GEN6_HIZ_OP_NONE:
 492       break;
 493    default:
 494       assert(0);
 495       break;
 496    }
 497    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 498    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 499    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 500    if (params->use_wm_prog) {
 501       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 502       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 503    }
 504
 505       if (params->num_samples > 1) {
 506          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 507          if (prog_data && prog_data->persample_msaa_dispatch)
 508             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 509          else
 510             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 511       } else {
 512          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 513          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 514       }
 515
 516    BEGIN_BATCH(3);
 517    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 518    OUT_BATCH(dw1);
 519    OUT_BATCH(dw2);
 520    ADVANCE_BATCH();
 521 }
 522
 523
 524 /**
 525  * 3DSTATE_PS
 526  *
 527  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 528  * that, thread dispatch info must still be specified.
 529  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 530  *       valid range for this field is [0x3, 0x2f].
 531  *     - A dispatch mode must be given; that is, at least one of the
 532  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 533  *       discovered through simulator error messages.
 534  */
 535 static void
 536 gen7_blorp_emit_ps_config(struct brw_context *brw,
 537                           const brw_blorp_params *params,
 538                           uint32_t prog_offset,
 539                           brw_blorp_prog_data *prog_data)
 540 {
 541    uint32_t dw2, dw4, dw5;
 542    const int max_threads_shift = brw->is_haswell ?
 543       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 544
 545    dw2 = dw4 = dw5 = 0;
 546    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 547
 548    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 549     * what the program is compiled for.  If there isn't, then it shouldn't
 550     * matter because no program is actually being run.  However, the hardware
 551     * gets angry if we don't enable at least one dispatch mode, so just enable
 552     * 16-pixel dispatch unconditionally.
 553     */
 554    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 555
 556    if (brw->is_haswell)
 557       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 558    if (params->use_wm_prog) {
 559       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 560       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 561       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 562    }
 563
 564    switch (params->fast_clear_op) {
 565    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 566       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 567       break;
 568    case GEN7_FAST_CLEAR_OP_RESOLVE:
 569       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 570       break;
 571    default:
 572       break;
 573    }
 574
 575    BEGIN_BATCH(8);
 576    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 577    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 578    OUT_BATCH(dw2);
 579    OUT_BATCH(0);
 580    OUT_BATCH(dw4);
 581    OUT_BATCH(dw5);
 582    OUT_BATCH(0);
 583    OUT_BATCH(0);
 584    ADVANCE_BATCH();
 585 }
 586
 587
 588 static void
 589 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 590                                           const brw_blorp_params *params,
 591                                           uint32_t wm_bind_bo_offset)
 592 {
 593    BEGIN_BATCH(2);
 594    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 595    OUT_BATCH(wm_bind_bo_offset);
 596    ADVANCE_BATCH();
 597 }
 598
 599
 600 static void
 601 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 602                                           const brw_blorp_params *params,
 603                                           uint32_t sampler_offset)
 604 {
 605    BEGIN_BATCH(2);
 606    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 607    OUT_BATCH(sampler_offset);
 608    ADVANCE_BATCH();
 609 }
 610
 611
 612 static void
 613 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 614                             const brw_blorp_params *params,
 615                             uint32_t wm_push_const_offset)
 616 {
 617    /* Make sure the push constants fill an exact integer number of
 618     * registers.
 619     */
 620    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 621
 622    /* There must be at least one register worth of push constant data. */
 623    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 624
 625    /* Enable push constant buffer 0. */
 626    BEGIN_BATCH(7);
 627    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 628              (7 - 2));
 629    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 630    OUT_BATCH(0);
 631    OUT_BATCH(wm_push_const_offset);
 632    OUT_BATCH(0);
 633    OUT_BATCH(0);
 634    OUT_BATCH(0);
 635    ADVANCE_BATCH();
 636 }
 637
 638 static void
 639 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 640                                     const brw_blorp_params *params)
 641 {
 642    BEGIN_BATCH(7);
 643    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 644    OUT_BATCH(0);
 645    OUT_BATCH(0);
 646    OUT_BATCH(0);
 647    OUT_BATCH(0);
 648    OUT_BATCH(0);
 649    OUT_BATCH(0);
 650    ADVANCE_BATCH();
 651 }
 652
 653 static void
 654 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 655                                      const brw_blorp_params *params)
 656 {
 657    struct gl_context *ctx = &brw->ctx;
 658    uint32_t draw_x = params->depth.x_offset;
 659    uint32_t draw_y = params->depth.y_offset;
 660    uint32_t tile_mask_x, tile_mask_y;
 661
 662    brw_get_depthstencil_tile_masks(params->depth.mt,
 663                                    params->depth.level,
 664                                    params->depth.layer,
 665                                    NULL,
 666                                    &tile_mask_x, &tile_mask_y);
 667
 668    /* 3DSTATE_DEPTH_BUFFER */
 669    {
 670       uint32_t tile_x = draw_x & tile_mask_x;
 671       uint32_t tile_y = draw_y & tile_mask_y;
 672       uint32_t offset =
 673          intel_region_get_aligned_offset(params->depth.mt->region,
 674                                          draw_x & ~tile_mask_x,
 675                                          draw_y & ~tile_mask_y, false);
 676
 677       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 678        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 679        * Coordinate Offset X/Y":
 680        *
 681        *   "The 3 LSBs of both offsets must be zero to ensure correct
 682        *   alignment"
 683        *
 684        * We have no guarantee that tile_x and tile_y are correctly aligned,
 685        * since they are determined by the mipmap layout, which is only aligned
 686        * to multiples of 4.
 687        *
 688        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 689        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 690        * up with a better solution.
 691        */
 692       WARN_ONCE((tile_x & 7) || (tile_y & 7),
 693                 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
 694                 "Truncating offset, bad rendering may occur.\n");
 695       tile_x &= ~7;
 696       tile_y &= ~7;
 697
 698       intel_emit_depth_stall_flushes(brw);
 699
 700       BEGIN_BATCH(7);
 701       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 702       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 703                 params->depth_format << 18 |
 704                 1 << 22 | /* hiz enable */
 705                 1 << 28 | /* depth write */
 706                 BRW_SURFACE_2D << 29);
 707       OUT_RELOC(params->depth.mt->region->bo,
 708                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 709                 offset);
 710       OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
 711                 (params->depth.height + tile_y - 1) << 18);
 712       OUT_BATCH(0);
 713       OUT_BATCH(tile_x |
 714                 tile_y << 16);
 715       OUT_BATCH(0);
 716       ADVANCE_BATCH();
 717    }
 718
 719    /* 3DSTATE_HIER_DEPTH_BUFFER */
 720    {
 721       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 722       uint32_t hiz_offset =
 723          intel_region_get_aligned_offset(hiz_region,
 724                                          draw_x & ~tile_mask_x,
 725                                          (draw_y & ~tile_mask_y) / 2, false);
 726
 727       BEGIN_BATCH(3);
 728       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 729       OUT_BATCH(hiz_region->pitch - 1);
 730       OUT_RELOC(hiz_region->bo,
 731                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 732                 hiz_offset);
 733       ADVANCE_BATCH();
 734    }
 735
 736    /* 3DSTATE_STENCIL_BUFFER */
 737    {
 738       BEGIN_BATCH(3);
 739       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 740       OUT_BATCH(0);
 741       OUT_BATCH(0);
 742       ADVANCE_BATCH();
 743    }
 744 }
 745
 746
 747 static void
 748 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 749                               const brw_blorp_params *params)
 750 {
 751    BEGIN_BATCH(7);
 752    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 753    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 754    OUT_BATCH(0);
 755    OUT_BATCH(0);
 756    OUT_BATCH(0);
 757    OUT_BATCH(0);
 758    OUT_BATCH(0);
 759    ADVANCE_BATCH();
 760 }
 761
 762
 763 /* 3DSTATE_CLEAR_PARAMS
 764  *
 765  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 766  * 3DSTATE_CLEAR_PARAMS:
 767  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 768  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 769  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 770  */
 771 static void
 772 gen7_blorp_emit_clear_params(struct brw_context *brw,
 773                              const brw_blorp_params *params)
 774 {
 775    BEGIN_BATCH(3);
 776    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 777    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 778    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 779    ADVANCE_BATCH();
 780 }
 781
 782
 783 /* 3DPRIMITIVE */
 784 static void
 785 gen7_blorp_emit_primitive(struct brw_context *brw,
 786                           const brw_blorp_params *params)
 787 {
 788    BEGIN_BATCH(7);
 789    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 790    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 791              _3DPRIM_RECTLIST);
 792    OUT_BATCH(3); /* vertex count per instance */
 793    OUT_BATCH(0);
 794    OUT_BATCH(1); /* instance count */
 795    OUT_BATCH(0);
 796    OUT_BATCH(0);
 797    ADVANCE_BATCH();
 798 }
 799
 800
 801 /**
 802  * \copydoc gen6_blorp_exec()
 803  */
 804 void
 805 gen7_blorp_exec(struct brw_context *brw,
 806                 const brw_blorp_params *params)
 807 {
 808    brw_blorp_prog_data *prog_data = NULL;
 809    uint32_t cc_blend_state_offset = 0;
 810    uint32_t cc_state_offset = 0;
 811    uint32_t depthstencil_offset;
 812    uint32_t wm_push_const_offset = 0;
 813    uint32_t wm_bind_bo_offset = 0;
 814    uint32_t sampler_offset = 0;
 815
 816    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 817    gen6_blorp_emit_batch_head(brw, params);
 818    gen6_emit_3dstate_multisample(brw, params->num_samples);
 819    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 820    gen6_blorp_emit_state_base_address(brw, params);
 821    gen6_blorp_emit_vertices(brw, params);
 822    gen7_blorp_emit_urb_config(brw, params);
 823    if (params->use_wm_prog) {
 824       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 825       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 826       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 827       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 828    }
 829    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 830    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 831                                                 depthstencil_offset);
 832    if (params->use_wm_prog) {
 833       uint32_t wm_surf_offset_renderbuffer;
 834       uint32_t wm_surf_offset_texture = 0;
 835       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 836       intel_miptree_used_for_rendering(params->dst.mt);
 837       wm_surf_offset_renderbuffer =
 838          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 839                                        I915_GEM_DOMAIN_RENDER,
 840                                        I915_GEM_DOMAIN_RENDER,
 841                                        true /* is_render_target */);
 842       if (params->src.mt) {
 843          wm_surf_offset_texture =
 844             gen7_blorp_emit_surface_state(brw, params, &params->src,
 845                                           I915_GEM_DOMAIN_SAMPLER, 0,
 846                                           false /* is_render_target */);
 847       }
 848       wm_bind_bo_offset =
 849          gen6_blorp_emit_binding_table(brw, params,
 850                                        wm_surf_offset_renderbuffer,
 851                                        wm_surf_offset_texture);
 852       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 853    }
 854    gen7_blorp_emit_vs_disable(brw, params);
 855    gen7_blorp_emit_hs_disable(brw, params);
 856    gen7_blorp_emit_te_disable(brw, params);
 857    gen7_blorp_emit_ds_disable(brw, params);
 858    gen7_blorp_emit_gs_disable(brw, params);
 859    gen7_blorp_emit_streamout_disable(brw, params);
 860    gen6_blorp_emit_clip_disable(brw, params);
 861    gen7_blorp_emit_sf_config(brw, params);
 862    gen7_blorp_emit_wm_config(brw, params, prog_data);
 863    if (params->use_wm_prog) {
 864       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 865                                                 wm_bind_bo_offset);
 866       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 867       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 868    } else {
 869       gen7_blorp_emit_constant_ps_disable(brw, params);
 870    }
 871    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 872    gen7_blorp_emit_cc_viewport(brw, params);
 873
 874    if (params->depth.mt)
 875       gen7_blorp_emit_depth_stencil_config(brw, params);
 876    else
 877       gen7_blorp_emit_depth_disable(brw, params);
 878    gen7_blorp_emit_clear_params(brw, params);
 879    gen6_blorp_emit_drawing_rectangle(brw, params);
 880    gen7_blorp_emit_primitive(brw, params);
 881 }