src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    struct intel_context *intel = &brw->intel;
  54
  55    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  56     * Dword 1.15:0 "VS Number of URB Entries".
  57     */
  58    int num_vs_entries = 32;
  59
  60    BEGIN_BATCH(2);
  61    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
  62    OUT_BATCH(1 << GEN7_URB_ENTRY_SIZE_SHIFT |
  63              0 << GEN7_URB_STARTING_ADDRESS_SHIFT |
  64              num_vs_entries);
  65    ADVANCE_BATCH();
  66
  67    BEGIN_BATCH(2);
  68    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
  69    OUT_BATCH(0);
  70    ADVANCE_BATCH();
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
  74    OUT_BATCH(0);
  75    ADVANCE_BATCH();
  76
  77    BEGIN_BATCH(2);
  78    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
  79    OUT_BATCH(0);
  80    ADVANCE_BATCH();
  81 }
  82
  83
  84 /* 3DSTATE_BLEND_STATE_POINTERS */
  85 static void
  86 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  87                                     const brw_blorp_params *params,
  88                                     uint32_t cc_blend_state_offset)
  89 {
  90    struct intel_context *intel = &brw->intel;
  91
  92    BEGIN_BATCH(2);
  93    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  94    OUT_BATCH(cc_blend_state_offset | 1);
  95    ADVANCE_BATCH();
  96 }
  97
  98
  99 /* 3DSTATE_CC_STATE_POINTERS */
 100 static void
 101 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 102                                  const brw_blorp_params *params,
 103                                  uint32_t cc_state_offset)
 104 {
 105    struct intel_context *intel = &brw->intel;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 109    OUT_BATCH(cc_state_offset | 1);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain)
 140 {
 141    struct intel_context *intel = &brw->intel;
 142
 143    uint32_t wm_surf_offset;
 144    uint32_t width, height;
 145    surface->get_miplevel_dims(&width, &height);
 146    if (surface->map_stencil_as_y_tiled) {
 147       width *= 2;
 148       height /= 2;
 149    }
 150    struct intel_region *region = surface->mt->region;
 151
 152    /* TODO: handle other formats */
 153    uint32_t format = surface->map_stencil_as_y_tiled
 154       ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 155
 156    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 157       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 158                       &wm_surf_offset);
 159    memset(surf, 0, sizeof(*surf));
 160
 161    if (surface->mt->align_h == 4)
 162       surf->ss0.vertical_alignment = 1;
 163    if (surface->mt->align_w == 8)
 164       surf->ss0.horizontal_alignment = 1;
 165
 166    surf->ss0.surface_format = format;
 167    surf->ss0.surface_type = BRW_SURFACE_2D;
 168
 169    /* reloc */
 170    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 171
 172    surf->ss2.width = width - 1;
 173    surf->ss2.height = height - 1;
 174
 175    uint32_t tiling = surface->map_stencil_as_y_tiled
 176       ? I915_TILING_Y : region->tiling;
 177    gen7_set_surface_tiling(surf, tiling);
 178
 179    uint32_t pitch_bytes = region->pitch * region->cpp;
 180    if (surface->map_stencil_as_y_tiled)
 181       pitch_bytes *= 2;
 182    surf->ss3.pitch = pitch_bytes - 1;
 183
 184    if (intel->is_haswell) {
 185       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 186       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 187       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 188       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 189    }
 190
 191    /* Emit relocation to surface contents */
 192    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 193                            wm_surf_offset +
 194                            offsetof(struct gen7_surface_state, ss1),
 195                            region->bo,
 196                            surf->ss1.base_addr - region->bo->offset,
 197                            read_domains, write_domain);
 198
 199    return wm_surf_offset;
 200 }
 201
 202
 203 /**
 204  * SAMPLER_STATE.  See gen7_update_sampler_state().
 205  */
 206 static uint32_t
 207 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 208                               const brw_blorp_params *params)
 209 {
 210    uint32_t sampler_offset;
 211
 212    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 213       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 214                       sizeof(struct gen7_sampler_state),
 215                       32, &sampler_offset);
 216    memset(sampler, 0, sizeof(*sampler));
 217
 218    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 219    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 220    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 221
 222    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 223    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 224    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 225
 226    //   sampler->ss0.min_mag_neq = 1;
 227
 228    /* Set LOD bias:
 229     */
 230    sampler->ss0.lod_bias = 0;
 231
 232    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 233    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 234
 235    /* Set BaseMipLevel, MaxLOD, MinLOD:
 236     *
 237     * XXX: I don't think that using firstLevel, lastLevel works,
 238     * because we always setup the surface state as if firstLevel ==
 239     * level zero.  Probably have to subtract firstLevel from each of
 240     * these:
 241     */
 242    sampler->ss0.base_level = U_FIXED(0, 1);
 243
 244    sampler->ss1.max_lod = U_FIXED(0, 8);
 245    sampler->ss1.min_lod = U_FIXED(0, 8);
 246
 247    sampler->ss3.non_normalized_coord = 1;
 248
 249    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 250       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 251       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 252    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 253       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 254       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 255
 256    return sampler_offset;
 257 }
 258
 259
 260 /* 3DSTATE_HS
 261  *
 262  * Disable the hull shader.
 263  */
 264 static void
 265 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 266                            const brw_blorp_params *params)
 267 {
 268    struct intel_context *intel = &brw->intel;
 269
 270    BEGIN_BATCH(7);
 271    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 272    OUT_BATCH(0);
 273    OUT_BATCH(0);
 274    OUT_BATCH(0);
 275    OUT_BATCH(0);
 276    OUT_BATCH(0);
 277    OUT_BATCH(0);
 278    ADVANCE_BATCH();
 279 }
 280
 281
 282 /* 3DSTATE_TE
 283  *
 284  * Disable the tesselation engine.
 285  */
 286 static void
 287 gen7_blorp_emit_te_disable(struct brw_context *brw,
 288                            const brw_blorp_params *params)
 289 {
 290    struct intel_context *intel = &brw->intel;
 291
 292    BEGIN_BATCH(4);
 293    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    ADVANCE_BATCH();
 298 }
 299
 300
 301 /* 3DSTATE_DS
 302  *
 303  * Disable the domain shader.
 304  */
 305 static void
 306 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 307                            const brw_blorp_params *params)
 308 {
 309    struct intel_context *intel = &brw->intel;
 310
 311    BEGIN_BATCH(6);
 312    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    ADVANCE_BATCH();
 319 }
 320
 321
 322 /* 3DSTATE_STREAMOUT
 323  *
 324  * Disable streamout.
 325  */
 326 static void
 327 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 328                                   const brw_blorp_params *params)
 329 {
 330    struct intel_context *intel = &brw->intel;
 331
 332    BEGIN_BATCH(3);
 333    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    ADVANCE_BATCH();
 337 }
 338
 339
 340 static void
 341 gen7_blorp_emit_sf_config(struct brw_context *brw,
 342                           const brw_blorp_params *params)
 343 {
 344    struct intel_context *intel = &brw->intel;
 345
 346    /* 3DSTATE_SF
 347     *
 348     * Disable ViewportTransformEnable (dw1.1)
 349     *
 350     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 351     * Primitives Overview":
 352     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 353     *     use of screen- space coordinates).
 354     *
 355     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 356     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 357     *
 358     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 359     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 360     *     SOLID: Any triangle or rectangle object found to be front-facing
 361     *     is rendered as a solid object. This setting is required when
 362     *     (rendering rectangle (RECTLIST) objects.
 363     */
 364    {
 365       BEGIN_BATCH(7);
 366       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 367       OUT_BATCH(params->depth_format <<
 368                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 369       OUT_BATCH(0);
 370       OUT_BATCH(0);
 371       OUT_BATCH(0);
 372       OUT_BATCH(0);
 373       OUT_BATCH(0);
 374       ADVANCE_BATCH();
 375    }
 376
 377    /* 3DSTATE_SBE */
 378    {
 379       BEGIN_BATCH(14);
 380       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 381       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 382                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 383                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 384       for (int i = 0; i < 12; ++i)
 385          OUT_BATCH(0);
 386       ADVANCE_BATCH();
 387    }
 388 }
 389
 390
 391 /**
 392  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 393  */
 394 static void
 395 gen7_blorp_emit_wm_config(struct brw_context *brw,
 396                           const brw_blorp_params *params)
 397 {
 398    struct intel_context *intel = &brw->intel;
 399
 400    uint32_t dw1 = 0;
 401
 402    switch (params->hiz_op) {
 403    case GEN6_HIZ_OP_DEPTH_CLEAR:
 404       assert(!"not implemented");
 405       dw1 |= GEN7_WM_DEPTH_CLEAR;
 406       break;
 407    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 408       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 409       break;
 410    case GEN6_HIZ_OP_HIZ_RESOLVE:
 411       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 412       break;
 413    default:
 414       assert(0);
 415       break;
 416    }
 417    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 418    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 419    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 420    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 421    if (params->use_wm_prog) {
 422       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 423       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 424    }
 425
 426    BEGIN_BATCH(3);
 427    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 428    OUT_BATCH(dw1);
 429    OUT_BATCH(0);
 430    ADVANCE_BATCH();
 431 }
 432
 433
 434 /**
 435  * 3DSTATE_PS
 436  *
 437  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 438  * that, thread dispatch info must still be specified.
 439  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 440  *       states that the valid range for this field is [0x3, 0x2f].
 441  *     - A dispatch mode must be given; that is, at least one of the
 442  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 443  *       discovered through simulator error messages.
 444  */
 445 static void
 446 gen7_blorp_emit_ps_config(struct brw_context *brw,
 447                           const brw_blorp_params *params,
 448                           uint32_t prog_offset,
 449                           brw_blorp_prog_data *prog_data)
 450 {
 451    struct intel_context *intel = &brw->intel;
 452    uint32_t dw2, dw4, dw5;
 453    const int max_threads_shift = brw->intel.is_haswell ?
 454       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 455
 456    dw2 = dw4 = dw5 = 0;
 457    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 458    dw4 |= GEN7_PS_32_DISPATCH_ENABLE;
 459    if (intel->is_haswell)
 460       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 461    if (params->use_wm_prog) {
 462       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 463       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 464       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 465    }
 466
 467    BEGIN_BATCH(8);
 468    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 469    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 470    OUT_BATCH(dw2);
 471    OUT_BATCH(0);
 472    OUT_BATCH(dw4);
 473    OUT_BATCH(dw5);
 474    OUT_BATCH(0);
 475    OUT_BATCH(0);
 476    ADVANCE_BATCH();
 477 }
 478
 479
 480 static void
 481 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 482                                           const brw_blorp_params *params,
 483                                           uint32_t wm_bind_bo_offset)
 484 {
 485    struct intel_context *intel = &brw->intel;
 486
 487    BEGIN_BATCH(2);
 488    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 489    OUT_BATCH(wm_bind_bo_offset);
 490    ADVANCE_BATCH();
 491 }
 492
 493
 494 static void
 495 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 496                                           const brw_blorp_params *params,
 497                                           uint32_t sampler_offset)
 498 {
 499    struct intel_context *intel = &brw->intel;
 500
 501    BEGIN_BATCH(2);
 502    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 503    OUT_BATCH(sampler_offset);
 504    ADVANCE_BATCH();
 505 }
 506
 507
 508 static void
 509 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 510                             const brw_blorp_params *params,
 511                             uint32_t wm_push_const_offset)
 512 {
 513    struct intel_context *intel = &brw->intel;
 514
 515    /* Make sure the push constants fill an exact integer number of
 516     * registers.
 517     */
 518    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 519
 520    /* There must be at least one register worth of push constant data. */
 521    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 522
 523    /* Enable push constant buffer 0. */
 524    BEGIN_BATCH(7);
 525    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 526              (7 - 2));
 527    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 528    OUT_BATCH(0);
 529    OUT_BATCH(wm_push_const_offset);
 530    OUT_BATCH(0);
 531    OUT_BATCH(0);
 532    OUT_BATCH(0);
 533    ADVANCE_BATCH();
 534 }
 535
 536
 537 static void
 538 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 539                                      const brw_blorp_params *params)
 540 {
 541    struct intel_context *intel = &brw->intel;
 542    uint32_t draw_x, draw_y;
 543    uint32_t tile_mask_x, tile_mask_y;
 544
 545    if (params->depth.mt) {
 546       params->depth.get_draw_offsets(&draw_x, &draw_y);
 547       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 548    }
 549
 550    /* 3DSTATE_DEPTH_BUFFER */
 551    {
 552       uint32_t width, height;
 553       params->depth.get_miplevel_dims(&width, &height);
 554
 555       uint32_t tile_x = draw_x & tile_mask_x;
 556       uint32_t tile_y = draw_y & tile_mask_y;
 557       uint32_t offset =
 558          intel_region_get_aligned_offset(params->depth.mt->region,
 559                                          draw_x & ~tile_mask_x,
 560                                          draw_y & ~tile_mask_y);
 561
 562       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 563        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 564        * Coordinate Offset X/Y":
 565        *
 566        *   "The 3 LSBs of both offsets must be zero to ensure correct
 567        *   alignment"
 568        *
 569        * We have no guarantee that tile_x and tile_y are correctly aligned,
 570        * since they are determined by the mipmap layout, which is only aligned
 571        * to multiples of 4.
 572        *
 573        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 574        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 575        * up with a better solution.
 576        */
 577       tile_x &= ~7;
 578       tile_y &= ~7;
 579
 580       intel_emit_depth_stall_flushes(intel);
 581
 582       BEGIN_BATCH(7);
 583       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 584       uint32_t pitch_bytes =
 585          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 586       OUT_BATCH((pitch_bytes - 1) |
 587                 params->depth_format << 18 |
 588                 1 << 22 | /* hiz enable */
 589                 1 << 28 | /* depth write */
 590                 BRW_SURFACE_2D << 29);
 591       OUT_RELOC(params->depth.mt->region->bo,
 592                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 593                 offset);
 594       OUT_BATCH((width + tile_x - 1) << 4 |
 595                 (height + tile_y - 1) << 18);
 596       OUT_BATCH(0);
 597       OUT_BATCH(tile_x |
 598                 tile_y << 16);
 599       OUT_BATCH(0);
 600       ADVANCE_BATCH();
 601    }
 602
 603    /* 3DSTATE_HIER_DEPTH_BUFFER */
 604    {
 605       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 606       uint32_t hiz_offset =
 607          intel_region_get_aligned_offset(hiz_region,
 608                                          draw_x & ~tile_mask_x,
 609                                          (draw_y & ~tile_mask_y) / 2);
 610
 611       BEGIN_BATCH(3);
 612       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 613       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 614       OUT_RELOC(hiz_region->bo,
 615                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 616                 hiz_offset);
 617       ADVANCE_BATCH();
 618    }
 619
 620    /* 3DSTATE_STENCIL_BUFFER */
 621    {
 622       BEGIN_BATCH(3);
 623       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 624       OUT_BATCH(0);
 625       OUT_BATCH(0);
 626       ADVANCE_BATCH();
 627    }
 628 }
 629
 630
 631 static void
 632 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 633                               const brw_blorp_params *params)
 634 {
 635    struct intel_context *intel = &brw->intel;
 636
 637    BEGIN_BATCH(7);
 638    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 639    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 640    OUT_BATCH(0);
 641    OUT_BATCH(0);
 642    OUT_BATCH(0);
 643    OUT_BATCH(0);
 644    OUT_BATCH(0);
 645    ADVANCE_BATCH();
 646 }
 647
 648
 649 /* 3DSTATE_CLEAR_PARAMS
 650  *
 651  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 652  * 3DSTATE_CLEAR_PARAMS:
 653  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 654  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 655  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 656  */
 657 static void
 658 gen7_blorp_emit_clear_params(struct brw_context *brw,
 659                              const brw_blorp_params *params)
 660 {
 661    struct intel_context *intel = &brw->intel;
 662
 663    BEGIN_BATCH(3);
 664    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 665    OUT_BATCH(0);
 666    OUT_BATCH(0);
 667    ADVANCE_BATCH();
 668 }
 669
 670
 671 /* 3DPRIMITIVE */
 672 static void
 673 gen7_blorp_emit_primitive(struct brw_context *brw,
 674                           const brw_blorp_params *params)
 675 {
 676    struct intel_context *intel = &brw->intel;
 677
 678    BEGIN_BATCH(7);
 679    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 680    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 681              _3DPRIM_RECTLIST);
 682    OUT_BATCH(3); /* vertex count per instance */
 683    OUT_BATCH(0);
 684    OUT_BATCH(1); /* instance count */
 685    OUT_BATCH(0);
 686    OUT_BATCH(0);
 687    ADVANCE_BATCH();
 688 }
 689
 690
 691 /**
 692  * \copydoc gen6_blorp_exec()
 693  */
 694 void
 695 gen7_blorp_exec(struct intel_context *intel,
 696                 const brw_blorp_params *params)
 697 {
 698    struct gl_context *ctx = &intel->ctx;
 699    struct brw_context *brw = brw_context(ctx);
 700    brw_blorp_prog_data *prog_data = NULL;
 701    uint32_t cc_blend_state_offset = 0;
 702    uint32_t cc_state_offset = 0;
 703    uint32_t depthstencil_offset;
 704    uint32_t wm_push_const_offset = 0;
 705    uint32_t wm_bind_bo_offset = 0;
 706    uint32_t sampler_offset = 0;
 707
 708    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 709    gen6_blorp_emit_batch_head(brw, params);
 710    gen6_blorp_emit_vertices(brw, params);
 711    gen7_blorp_emit_urb_config(brw, params);
 712    if (params->use_wm_prog) {
 713       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 714       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 715       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 716       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 717    }
 718    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 719    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 720                                                 depthstencil_offset);
 721    if (params->use_wm_prog) {
 722       uint32_t wm_surf_offset_renderbuffer;
 723       uint32_t wm_surf_offset_texture;
 724       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 725       wm_surf_offset_renderbuffer =
 726          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 727                                        I915_GEM_DOMAIN_RENDER,
 728                                        I915_GEM_DOMAIN_RENDER);
 729       wm_surf_offset_texture =
 730          gen7_blorp_emit_surface_state(brw, params, &params->src,
 731                                        I915_GEM_DOMAIN_SAMPLER, 0);
 732       wm_bind_bo_offset =
 733          gen6_blorp_emit_binding_table(brw, params,
 734                                        wm_surf_offset_renderbuffer,
 735                                        wm_surf_offset_texture);
 736       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 737    }
 738    gen6_blorp_emit_vs_disable(brw, params);
 739    gen7_blorp_emit_hs_disable(brw, params);
 740    gen7_blorp_emit_te_disable(brw, params);
 741    gen7_blorp_emit_ds_disable(brw, params);
 742    gen6_blorp_emit_gs_disable(brw, params);
 743    gen7_blorp_emit_streamout_disable(brw, params);
 744    gen6_blorp_emit_clip_disable(brw, params);
 745    gen7_blorp_emit_sf_config(brw, params);
 746    gen7_blorp_emit_wm_config(brw, params);
 747    if (params->use_wm_prog) {
 748       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 749                                                 wm_bind_bo_offset);
 750       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 751       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 752    }
 753    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 754
 755    if (params->depth.mt)
 756       gen7_blorp_emit_depth_stencil_config(brw, params);
 757    else
 758       gen7_blorp_emit_depth_disable(brw, params);
 759    gen7_blorp_emit_clear_params(brw, params);
 760    gen6_blorp_emit_drawing_rectangle(brw, params);
 761    gen7_blorp_emit_primitive(brw, params);
 762
 763    /* See comments above at first invocation of intel_flush() in
 764     * gen6_blorp_emit_batch_head().
 765     */
 766    intel_flush(ctx);
 767
 768    /* Be safe. */
 769    brw->state.dirty.brw = ~0;
 770    brw->state.dirty.cache = ~0;
 771 }
 772
 773 /** \copydoc gen6_resolve_hiz_slice() */
 774 void
 775 gen7_resolve_hiz_slice(struct intel_context *intel,
 776                        struct intel_mipmap_tree *mt,
 777                        uint32_t level,
 778                        uint32_t layer)
 779 {
 780    brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
 781    gen7_blorp_exec(intel, &params);
 782 }
 783
 784 /** \copydoc gen6_resolve_depth_slice() */
 785 void
 786 gen7_resolve_depth_slice(struct intel_context *intel,
 787                          struct intel_mipmap_tree *mt,
 788                          uint32_t level,
 789                          uint32_t layer)
 790 {
 791    brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
 792    gen7_blorp_exec(intel, &params);
 793 }