src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  44  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  45  *
  46  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  47  *     programmed in order for the programming of this state to be
  48  *     valid.
  49  */
  50 static void
  51 gen7_blorp_emit_urb_config(struct brw_context *brw,
  52                            const brw_blorp_params *params)
  53 {
  54    unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
  55    gen7_emit_push_constant_state(brw,
  56                                  urb_size / 2 /* vs_size */,
  57                                  0 /* gs_size */,
  58                                  urb_size / 2 /* fs_size */);
  59
  60    /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
  61     * 1.15:0 "VS Number of URB Entries".
  62     */
  63    gen7_emit_urb_state(brw,
  64                        32 /* num_vs_entries */,
  65                        2 /* vs_size */,
  66                        2 /* vs_start */,
  67                        0 /* num_gs_entries */,
  68                        1 /* gs_size */,
  69                        2 /* gs_start */);
  70 }
  71
  72
  73 /* 3DSTATE_BLEND_STATE_POINTERS */
  74 static void
  75 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  76                                     const brw_blorp_params *params,
  77                                     uint32_t cc_blend_state_offset)
  78 {
  79    BEGIN_BATCH(2);
  80    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  81    OUT_BATCH(cc_blend_state_offset | 1);
  82    ADVANCE_BATCH();
  83 }
  84
  85
  86 /* 3DSTATE_CC_STATE_POINTERS */
  87 static void
  88 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  89                                  const brw_blorp_params *params,
  90                                  uint32_t cc_state_offset)
  91 {
  92    BEGIN_BATCH(2);
  93    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  94    OUT_BATCH(cc_state_offset | 1);
  95    ADVANCE_BATCH();
  96 }
  97
  98 static void
  99 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
 100                             const brw_blorp_params *params)
 101 {
 102    struct brw_cc_viewport *ccv;
 103    uint32_t cc_vp_offset;
 104
 105    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 106                                                    sizeof(*ccv), 32,
 107                                                    &cc_vp_offset);
 108    ccv->min_depth = 0.0;
 109    ccv->max_depth = 1.0;
 110
 111    BEGIN_BATCH(2);
 112    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 113    OUT_BATCH(cc_vp_offset);
 114    ADVANCE_BATCH();
 115 }
 116
 117
 118 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 119  *
 120  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 121  */
 122 static void
 123 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 124                                              const brw_blorp_params *params,
 125                                              uint32_t depthstencil_offset)
 126 {
 127    BEGIN_BATCH(2);
 128    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 129    OUT_BATCH(depthstencil_offset | 1);
 130    ADVANCE_BATCH();
 131 }
 132
 133
 134 /* SURFACE_STATE for renderbuffer or texture surface (see
 135  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 136  */
 137 static uint32_t
 138 gen7_blorp_emit_surface_state(struct brw_context *brw,
 139                               const brw_blorp_params *params,
 140                               const brw_blorp_surface_info *surface,
 141                               uint32_t read_domains, uint32_t write_domain,
 142                               bool is_render_target)
 143 {
 144    uint32_t wm_surf_offset;
 145    uint32_t width = surface->width;
 146    uint32_t height = surface->height;
 147    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 148     * color surfaces, width and height are measured in pixels; we don't need
 149     * to divide them by 2 as we do for Gen6 (see
 150     * gen6_blorp_emit_surface_state).
 151     */
 152    struct intel_region *region = surface->mt->region;
 153    uint32_t tile_x, tile_y;
 154    const uint8_t mocs = GEN7_MOCS_L3;
 155
 156    uint32_t tiling = surface->map_stencil_as_y_tiled
 157       ? I915_TILING_Y : region->tiling;
 158
 159    uint32_t *surf = (uint32_t *)
 160       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 161    memset(surf, 0, 8 * 4);
 162
 163    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 164              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 165              gen7_surface_tiling_mode(tiling);
 166
 167    if (surface->mt->align_h == 4)
 168       surf[0] |= GEN7_SURFACE_VALIGN_4;
 169    if (surface->mt->align_w == 8)
 170       surf[0] |= GEN7_SURFACE_HALIGN_8;
 171
 172    if (surface->array_spacing_lod0)
 173       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 174    else
 175       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 176
 177    /* reloc */
 178    surf[1] =
 179       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 180
 181    /* Note that the low bits of these fields are missing, so
 182     * there's the possibility of getting in trouble.
 183     */
 184    assert(tile_x % 4 == 0);
 185    assert(tile_y % 2 == 0);
 186    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 187              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 188              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 189
 190    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 191              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 192
 193    uint32_t pitch_bytes = region->pitch;
 194    if (surface->map_stencil_as_y_tiled)
 195       pitch_bytes *= 2;
 196    surf[3] = pitch_bytes - 1;
 197
 198    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 199    if (surface->mt->mcs_mt) {
 200       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 201                                 is_render_target);
 202    }
 203
 204    surf[7] = surface->mt->fast_clear_color_value;
 205
 206    if (brw->is_haswell) {
 207       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 208                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 209                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 210                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 211    }
 212
 213    /* Emit relocation to surface contents */
 214    drm_intel_bo_emit_reloc(brw->batch.bo,
 215                            wm_surf_offset + 4,
 216                            region->bo,
 217                            surf[1] - region->bo->offset,
 218                            read_domains, write_domain);
 219
 220    gen7_check_surface_setup(surf, is_render_target);
 221
 222    return wm_surf_offset;
 223 }
 224
 225
 226 /**
 227  * SAMPLER_STATE.  See gen7_update_sampler_state().
 228  */
 229 static uint32_t
 230 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 231                               const brw_blorp_params *params)
 232 {
 233    uint32_t sampler_offset;
 234
 235    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 236       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 237                       sizeof(struct gen7_sampler_state),
 238                       32, &sampler_offset);
 239    memset(sampler, 0, sizeof(*sampler));
 240
 241    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 242    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 243    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 244
 245    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 246    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 247    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 248
 249    //   sampler->ss0.min_mag_neq = 1;
 250
 251    /* Set LOD bias:
 252     */
 253    sampler->ss0.lod_bias = 0;
 254
 255    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 256    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 257
 258    /* Set BaseMipLevel, MaxLOD, MinLOD:
 259     *
 260     * XXX: I don't think that using firstLevel, lastLevel works,
 261     * because we always setup the surface state as if firstLevel ==
 262     * level zero.  Probably have to subtract firstLevel from each of
 263     * these:
 264     */
 265    sampler->ss0.base_level = U_FIXED(0, 1);
 266
 267    sampler->ss1.max_lod = U_FIXED(0, 8);
 268    sampler->ss1.min_lod = U_FIXED(0, 8);
 269
 270    sampler->ss3.non_normalized_coord = 1;
 271
 272    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 273       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 274       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 275    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 276       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 277       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 278
 279    return sampler_offset;
 280 }
 281
 282
 283 /* 3DSTATE_VS
 284  *
 285  * Disable vertex shader.
 286  */
 287 static void
 288 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 289                            const brw_blorp_params *params)
 290 {
 291    BEGIN_BATCH(7);
 292    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 293    OUT_BATCH(0);
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    ADVANCE_BATCH();
 300
 301    BEGIN_BATCH(6);
 302    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 303    OUT_BATCH(0);
 304    OUT_BATCH(0);
 305    OUT_BATCH(0);
 306    OUT_BATCH(0);
 307    OUT_BATCH(0);
 308    ADVANCE_BATCH();
 309 }
 310
 311
 312 /* 3DSTATE_HS
 313  *
 314  * Disable the hull shader.
 315  */
 316 static void
 317 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 318                            const brw_blorp_params *params)
 319 {
 320    BEGIN_BATCH(7);
 321    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    ADVANCE_BATCH();
 329
 330    BEGIN_BATCH(7);
 331    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 332    OUT_BATCH(0);
 333    OUT_BATCH(0);
 334    OUT_BATCH(0);
 335    OUT_BATCH(0);
 336    OUT_BATCH(0);
 337    OUT_BATCH(0);
 338    ADVANCE_BATCH();
 339 }
 340
 341
 342 /* 3DSTATE_TE
 343  *
 344  * Disable the tesselation engine.
 345  */
 346 static void
 347 gen7_blorp_emit_te_disable(struct brw_context *brw,
 348                            const brw_blorp_params *params)
 349 {
 350    BEGIN_BATCH(4);
 351    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 352    OUT_BATCH(0);
 353    OUT_BATCH(0);
 354    OUT_BATCH(0);
 355    ADVANCE_BATCH();
 356 }
 357
 358
 359 /* 3DSTATE_DS
 360  *
 361  * Disable the domain shader.
 362  */
 363 static void
 364 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 365                            const brw_blorp_params *params)
 366 {
 367    BEGIN_BATCH(7);
 368    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 369    OUT_BATCH(0);
 370    OUT_BATCH(0);
 371    OUT_BATCH(0);
 372    OUT_BATCH(0);
 373    OUT_BATCH(0);
 374    OUT_BATCH(0);
 375    ADVANCE_BATCH();
 376
 377    BEGIN_BATCH(6);
 378    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 379    OUT_BATCH(0);
 380    OUT_BATCH(0);
 381    OUT_BATCH(0);
 382    OUT_BATCH(0);
 383    OUT_BATCH(0);
 384    ADVANCE_BATCH();
 385 }
 386
 387 /* 3DSTATE_GS
 388  *
 389  * Disable the geometry shader.
 390  */
 391 static void
 392 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 393                            const brw_blorp_params *params)
 394 {
 395    BEGIN_BATCH(7);
 396    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 397    OUT_BATCH(0);
 398    OUT_BATCH(0);
 399    OUT_BATCH(0);
 400    OUT_BATCH(0);
 401    OUT_BATCH(0);
 402    OUT_BATCH(0);
 403    ADVANCE_BATCH();
 404
 405    BEGIN_BATCH(7);
 406    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 407    OUT_BATCH(0);
 408    OUT_BATCH(0);
 409    OUT_BATCH(0);
 410    OUT_BATCH(0);
 411    OUT_BATCH(0);
 412    OUT_BATCH(0);
 413    ADVANCE_BATCH();
 414 }
 415
 416 /* 3DSTATE_STREAMOUT
 417  *
 418  * Disable streamout.
 419  */
 420 static void
 421 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 422                                   const brw_blorp_params *params)
 423 {
 424    BEGIN_BATCH(3);
 425    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 426    OUT_BATCH(0);
 427    OUT_BATCH(0);
 428    ADVANCE_BATCH();
 429 }
 430
 431
 432 static void
 433 gen7_blorp_emit_sf_config(struct brw_context *brw,
 434                           const brw_blorp_params *params)
 435 {
 436    /* 3DSTATE_SF
 437     *
 438     * Disable ViewportTransformEnable (dw1.1)
 439     *
 440     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 441     * Primitives Overview":
 442     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 443     *     use of screen- space coordinates).
 444     *
 445     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 446     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 447     *
 448     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 449     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 450     *     SOLID: Any triangle or rectangle object found to be front-facing
 451     *     is rendered as a solid object. This setting is required when
 452     *     (rendering rectangle (RECTLIST) objects.
 453     */
 454    {
 455       BEGIN_BATCH(7);
 456       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 457       OUT_BATCH(params->depth_format <<
 458                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 459       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 460       OUT_BATCH(0);
 461       OUT_BATCH(0);
 462       OUT_BATCH(0);
 463       OUT_BATCH(0);
 464       ADVANCE_BATCH();
 465    }
 466
 467    /* 3DSTATE_SBE */
 468    {
 469       BEGIN_BATCH(14);
 470       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 471       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 472                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 473                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 474       for (int i = 0; i < 12; ++i)
 475          OUT_BATCH(0);
 476       ADVANCE_BATCH();
 477    }
 478 }
 479
 480
 481 /**
 482  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 483  */
 484 static void
 485 gen7_blorp_emit_wm_config(struct brw_context *brw,
 486                           const brw_blorp_params *params,
 487                           brw_blorp_prog_data *prog_data)
 488 {
 489    uint32_t dw1 = 0, dw2 = 0;
 490
 491    switch (params->hiz_op) {
 492    case GEN6_HIZ_OP_DEPTH_CLEAR:
 493       dw1 |= GEN7_WM_DEPTH_CLEAR;
 494       break;
 495    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 496       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 497       break;
 498    case GEN6_HIZ_OP_HIZ_RESOLVE:
 499       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 500       break;
 501    case GEN6_HIZ_OP_NONE:
 502       break;
 503    default:
 504       assert(0);
 505       break;
 506    }
 507    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 508    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 509    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 510    if (params->use_wm_prog) {
 511       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 512       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 513    }
 514
 515       if (params->num_samples > 1) {
 516          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 517          if (prog_data && prog_data->persample_msaa_dispatch)
 518             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 519          else
 520             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 521       } else {
 522          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 523          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 524       }
 525
 526    BEGIN_BATCH(3);
 527    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 528    OUT_BATCH(dw1);
 529    OUT_BATCH(dw2);
 530    ADVANCE_BATCH();
 531 }
 532
 533
 534 /**
 535  * 3DSTATE_PS
 536  *
 537  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 538  * that, thread dispatch info must still be specified.
 539  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 540  *       valid range for this field is [0x3, 0x2f].
 541  *     - A dispatch mode must be given; that is, at least one of the
 542  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 543  *       discovered through simulator error messages.
 544  */
 545 static void
 546 gen7_blorp_emit_ps_config(struct brw_context *brw,
 547                           const brw_blorp_params *params,
 548                           uint32_t prog_offset,
 549                           brw_blorp_prog_data *prog_data)
 550 {
 551    uint32_t dw2, dw4, dw5;
 552    const int max_threads_shift = brw->is_haswell ?
 553       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 554
 555    dw2 = dw4 = dw5 = 0;
 556    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 557
 558    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 559     * what the program is compiled for.  If there isn't, then it shouldn't
 560     * matter because no program is actually being run.  However, the hardware
 561     * gets angry if we don't enable at least one dispatch mode, so just enable
 562     * 16-pixel dispatch unconditionally.
 563     */
 564    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 565
 566    if (brw->is_haswell)
 567       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 568    if (params->use_wm_prog) {
 569       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 570       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 571       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 572    }
 573
 574    switch (params->fast_clear_op) {
 575    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 576       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 577       break;
 578    case GEN7_FAST_CLEAR_OP_RESOLVE:
 579       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 580       break;
 581    default:
 582       break;
 583    }
 584
 585    BEGIN_BATCH(8);
 586    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 587    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 588    OUT_BATCH(dw2);
 589    OUT_BATCH(0);
 590    OUT_BATCH(dw4);
 591    OUT_BATCH(dw5);
 592    OUT_BATCH(0);
 593    OUT_BATCH(0);
 594    ADVANCE_BATCH();
 595 }
 596
 597
 598 static void
 599 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 600                                           const brw_blorp_params *params,
 601                                           uint32_t wm_bind_bo_offset)
 602 {
 603    BEGIN_BATCH(2);
 604    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 605    OUT_BATCH(wm_bind_bo_offset);
 606    ADVANCE_BATCH();
 607 }
 608
 609
 610 static void
 611 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 612                                           const brw_blorp_params *params,
 613                                           uint32_t sampler_offset)
 614 {
 615    BEGIN_BATCH(2);
 616    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 617    OUT_BATCH(sampler_offset);
 618    ADVANCE_BATCH();
 619 }
 620
 621
 622 static void
 623 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 624                             const brw_blorp_params *params,
 625                             uint32_t wm_push_const_offset)
 626 {
 627    const uint8_t mocs = GEN7_MOCS_L3;
 628
 629    /* Make sure the push constants fill an exact integer number of
 630     * registers.
 631     */
 632    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 633
 634    /* There must be at least one register worth of push constant data. */
 635    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 636
 637    /* Enable push constant buffer 0. */
 638    BEGIN_BATCH(7);
 639    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 640              (7 - 2));
 641    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 642    OUT_BATCH(0);
 643    OUT_BATCH(wm_push_const_offset | mocs);
 644    OUT_BATCH(0);
 645    OUT_BATCH(0);
 646    OUT_BATCH(0);
 647    ADVANCE_BATCH();
 648 }
 649
 650 static void
 651 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 652                                     const brw_blorp_params *params)
 653 {
 654    BEGIN_BATCH(7);
 655    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 656    OUT_BATCH(0);
 657    OUT_BATCH(0);
 658    OUT_BATCH(0);
 659    OUT_BATCH(0);
 660    OUT_BATCH(0);
 661    OUT_BATCH(0);
 662    ADVANCE_BATCH();
 663 }
 664
 665 static void
 666 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 667                                      const brw_blorp_params *params)
 668 {
 669    const uint8_t mocs = GEN7_MOCS_L3;
 670    uint32_t surfwidth, surfheight;
 671    uint32_t surftype;
 672    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 673    unsigned int min_array_element;
 674    GLenum gl_target = params->depth.mt->target;
 675    unsigned int lod;
 676
 677    switch (gl_target) {
 678    case GL_TEXTURE_CUBE_MAP_ARRAY:
 679    case GL_TEXTURE_CUBE_MAP:
 680       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 681        * situation, but experiments show that gl_Layer doesn't work when we do
 682        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 683        * equivalent.
 684        */
 685       surftype = BRW_SURFACE_2D;
 686       depth *= 6;
 687       break;
 688    default:
 689       surftype = translate_tex_target(gl_target);
 690       break;
 691    }
 692
 693    min_array_element = params->depth.layer;
 694    if (params->depth.mt->num_samples > 1) {
 695       /* Convert physical layer to logical layer. */
 696       min_array_element /= params->depth.mt->num_samples;
 697    }
 698
 699    lod = params->depth.level - params->depth.mt->first_level;
 700
 701    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 702       /* HIZ ops for lod 0 may set the width & height a little
 703        * larger to allow the fast depth clear to fit the hardware
 704        * alignment requirements. (8x4)
 705        */
 706       surfwidth = params->depth.width;
 707       surfheight = params->depth.height;
 708    } else {
 709       surfwidth = params->depth.mt->logical_width0;
 710       surfheight = params->depth.mt->logical_height0;
 711    }
 712
 713    /* 3DSTATE_DEPTH_BUFFER */
 714    {
 715       intel_emit_depth_stall_flushes(brw);
 716
 717       BEGIN_BATCH(7);
 718       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 719       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 720                 params->depth_format << 18 |
 721                 1 << 22 | /* hiz enable */
 722                 1 << 28 | /* depth write */
 723                 surftype << 29);
 724       OUT_RELOC(params->depth.mt->region->bo,
 725                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 726                 0);
 727       OUT_BATCH((surfwidth - 1) << 4 |
 728                 (surfheight - 1) << 18 |
 729                 lod);
 730       OUT_BATCH(((depth - 1) << 21) |
 731                 (min_array_element << 10) |
 732                 mocs);
 733       OUT_BATCH(0);
 734       OUT_BATCH((depth - 1) << 21);
 735       ADVANCE_BATCH();
 736    }
 737
 738    /* 3DSTATE_HIER_DEPTH_BUFFER */
 739    {
 740       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 741
 742       BEGIN_BATCH(3);
 743       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 744       OUT_BATCH((mocs << 25) |
 745                 (hiz_region->pitch - 1));
 746       OUT_RELOC(hiz_region->bo,
 747                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 748                 0);
 749       ADVANCE_BATCH();
 750    }
 751
 752    /* 3DSTATE_STENCIL_BUFFER */
 753    {
 754       BEGIN_BATCH(3);
 755       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 756       OUT_BATCH(0);
 757       OUT_BATCH(0);
 758       ADVANCE_BATCH();
 759    }
 760 }
 761
 762
 763 static void
 764 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 765                               const brw_blorp_params *params)
 766 {
 767    intel_emit_depth_stall_flushes(brw);
 768
 769    BEGIN_BATCH(7);
 770    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 771    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 772    OUT_BATCH(0);
 773    OUT_BATCH(0);
 774    OUT_BATCH(0);
 775    OUT_BATCH(0);
 776    OUT_BATCH(0);
 777    ADVANCE_BATCH();
 778 }
 779
 780
 781 /* 3DSTATE_CLEAR_PARAMS
 782  *
 783  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 784  * 3DSTATE_CLEAR_PARAMS:
 785  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 786  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 787  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 788  */
 789 static void
 790 gen7_blorp_emit_clear_params(struct brw_context *brw,
 791                              const brw_blorp_params *params)
 792 {
 793    BEGIN_BATCH(3);
 794    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 795    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 796    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 797    ADVANCE_BATCH();
 798 }
 799
 800
 801 /* 3DPRIMITIVE */
 802 static void
 803 gen7_blorp_emit_primitive(struct brw_context *brw,
 804                           const brw_blorp_params *params)
 805 {
 806    BEGIN_BATCH(7);
 807    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 808    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 809              _3DPRIM_RECTLIST);
 810    OUT_BATCH(3); /* vertex count per instance */
 811    OUT_BATCH(0);
 812    OUT_BATCH(1); /* instance count */
 813    OUT_BATCH(0);
 814    OUT_BATCH(0);
 815    ADVANCE_BATCH();
 816 }
 817
 818
 819 /**
 820  * \copydoc gen6_blorp_exec()
 821  */
 822 void
 823 gen7_blorp_exec(struct brw_context *brw,
 824                 const brw_blorp_params *params)
 825 {
 826    brw_blorp_prog_data *prog_data = NULL;
 827    uint32_t cc_blend_state_offset = 0;
 828    uint32_t cc_state_offset = 0;
 829    uint32_t depthstencil_offset;
 830    uint32_t wm_push_const_offset = 0;
 831    uint32_t wm_bind_bo_offset = 0;
 832    uint32_t sampler_offset = 0;
 833
 834    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 835    gen6_blorp_emit_batch_head(brw, params);
 836    gen6_emit_3dstate_multisample(brw, params->num_samples);
 837    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 838    gen6_blorp_emit_state_base_address(brw, params);
 839    gen6_blorp_emit_vertices(brw, params);
 840    gen7_blorp_emit_urb_config(brw, params);
 841    if (params->use_wm_prog) {
 842       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 843       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 844       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 845       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 846    }
 847    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 848    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 849                                                 depthstencil_offset);
 850    if (params->use_wm_prog) {
 851       uint32_t wm_surf_offset_renderbuffer;
 852       uint32_t wm_surf_offset_texture = 0;
 853       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 854       intel_miptree_used_for_rendering(params->dst.mt);
 855       wm_surf_offset_renderbuffer =
 856          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 857                                        I915_GEM_DOMAIN_RENDER,
 858                                        I915_GEM_DOMAIN_RENDER,
 859                                        true /* is_render_target */);
 860       if (params->src.mt) {
 861          wm_surf_offset_texture =
 862             gen7_blorp_emit_surface_state(brw, params, &params->src,
 863                                           I915_GEM_DOMAIN_SAMPLER, 0,
 864                                           false /* is_render_target */);
 865       }
 866       wm_bind_bo_offset =
 867          gen6_blorp_emit_binding_table(brw, params,
 868                                        wm_surf_offset_renderbuffer,
 869                                        wm_surf_offset_texture);
 870       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 871    }
 872    gen7_blorp_emit_vs_disable(brw, params);
 873    gen7_blorp_emit_hs_disable(brw, params);
 874    gen7_blorp_emit_te_disable(brw, params);
 875    gen7_blorp_emit_ds_disable(brw, params);
 876    gen7_blorp_emit_gs_disable(brw, params);
 877    gen7_blorp_emit_streamout_disable(brw, params);
 878    gen6_blorp_emit_clip_disable(brw, params);
 879    gen7_blorp_emit_sf_config(brw, params);
 880    gen7_blorp_emit_wm_config(brw, params, prog_data);
 881    if (params->use_wm_prog) {
 882       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 883                                                 wm_bind_bo_offset);
 884       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 885       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 886    } else {
 887       gen7_blorp_emit_constant_ps_disable(brw, params);
 888    }
 889    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 890    gen7_blorp_emit_cc_viewport(brw, params);
 891
 892    if (params->depth.mt)
 893       gen7_blorp_emit_depth_stencil_config(brw, params);
 894    else
 895       gen7_blorp_emit_depth_disable(brw, params);
 896    gen7_blorp_emit_clear_params(brw, params);
 897    gen6_blorp_emit_drawing_rectangle(brw, params);
 898    gen7_blorp_emit_primitive(brw, params);
 899 }