src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "brw_blorp.h"
  33
  34
  35 /* 3DSTATE_URB_VS
  36  * 3DSTATE_URB_HS
  37  * 3DSTATE_URB_DS
  38  * 3DSTATE_URB_GS
  39  *
  40  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  41  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  42  *
  43  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  44  *     programmed in order for the programming of this state to be
  45  *     valid.
  46  */
  47 void
  48 gen7_blorp_emit_urb_config(struct brw_context *brw)
  49 {
  50    /* URB allocations must be done in 8k chunks. */
  51    const unsigned chunk_size_bytes = 8192;
  52    const unsigned urb_size =
  53       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
  54    const unsigned push_constant_bytes = 1024 * urb_size;
  55    const unsigned push_constant_chunks =
  56       push_constant_bytes / chunk_size_bytes;
  57    const unsigned vs_size = 2;
  58    const unsigned vs_start = push_constant_chunks;
  59    const unsigned vs_chunks =
  60       DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes);
  61
  62    gen7_emit_push_constant_state(brw,
  63                                  urb_size / 2 /* vs_size */,
  64                                  0 /* hs_size */,
  65                                  0 /* ds_size */,
  66                                  0 /* gs_size */,
  67                                  urb_size / 2 /* fs_size */);
  68
  69    gen7_emit_urb_state(brw,
  70                        brw->urb.min_vs_entries /* num_vs_entries */,
  71                        vs_size,
  72                        vs_start,
  73                        0 /* num_hs_entries */,
  74                        1 /* hs_size */,
  75                        vs_start + vs_chunks /* hs_start */,
  76                        0 /* num_ds_entries */,
  77                        1 /* ds_size */,
  78                        vs_start + vs_chunks /* ds_start */,
  79                        0 /* num_gs_entries */,
  80                        1 /* gs_size */,
  81                        vs_start + vs_chunks /* gs_start */);
  82 }
  83
  84
  85 /* 3DSTATE_BLEND_STATE_POINTERS */
  86 void
  87 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  88                                     uint32_t cc_blend_state_offset)
  89 {
  90    BEGIN_BATCH(2);
  91    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  92    OUT_BATCH(cc_blend_state_offset | 1);
  93    ADVANCE_BATCH();
  94 }
  95
  96
  97 /* 3DSTATE_CC_STATE_POINTERS */
  98 void
  99 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 100                                  uint32_t cc_state_offset)
 101 {
 102    BEGIN_BATCH(2);
 103    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 104    OUT_BATCH(cc_state_offset | 1);
 105    ADVANCE_BATCH();
 106 }
 107
 108 void
 109 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 110 {
 111    struct brw_cc_viewport *ccv;
 112    uint32_t cc_vp_offset;
 113
 114    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 115                                                    sizeof(*ccv), 32,
 116                                                    &cc_vp_offset);
 117    ccv->min_depth = 0.0;
 118    ccv->max_depth = 1.0;
 119
 120    BEGIN_BATCH(2);
 121    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 122    OUT_BATCH(cc_vp_offset);
 123    ADVANCE_BATCH();
 124 }
 125
 126
 127 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 128  *
 129  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 130  */
 131 static void
 132 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 133                                              uint32_t depthstencil_offset)
 134 {
 135    BEGIN_BATCH(2);
 136    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 137    OUT_BATCH(depthstencil_offset | 1);
 138    ADVANCE_BATCH();
 139 }
 140
 141
 142 /* SURFACE_STATE for renderbuffer or texture surface (see
 143  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 144  */
 145 static uint32_t
 146 gen7_blorp_emit_surface_state(struct brw_context *brw,
 147                               const brw_blorp_surface_info *surface,
 148                               uint32_t read_domains, uint32_t write_domain,
 149                               bool is_render_target)
 150 {
 151    uint32_t wm_surf_offset;
 152    uint32_t width = surface->width;
 153    uint32_t height = surface->height;
 154    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 155     * color surfaces, width and height are measured in pixels; we don't need
 156     * to divide them by 2 as we do for Gen6 (see
 157     * gen6_blorp_emit_surface_state).
 158     */
 159    struct intel_mipmap_tree *mt = surface->mt;
 160    uint32_t tile_x, tile_y;
 161    const uint8_t mocs = GEN7_MOCS_L3;
 162
 163    uint32_t tiling = surface->map_stencil_as_y_tiled
 164       ? I915_TILING_Y : mt->tiling;
 165
 166    uint32_t *surf = (uint32_t *)
 167       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 168    memset(surf, 0, 8 * 4);
 169
 170    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 171              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 172              gen7_surface_tiling_mode(tiling);
 173
 174    if (surface->mt->valign == 4)
 175       surf[0] |= GEN7_SURFACE_VALIGN_4;
 176    if (surface->mt->halign == 8)
 177       surf[0] |= GEN7_SURFACE_HALIGN_8;
 178
 179    if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
 180       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 181    else
 182       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 183
 184    /* reloc */
 185    surf[1] =
 186       surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
 187
 188    /* Note that the low bits of these fields are missing, so
 189     * there's the possibility of getting in trouble.
 190     */
 191    assert(tile_x % 4 == 0);
 192    assert(tile_y % 2 == 0);
 193    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 194              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 195              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 196
 197    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 198              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 199
 200    uint32_t pitch_bytes = mt->pitch;
 201    if (surface->map_stencil_as_y_tiled)
 202       pitch_bytes *= 2;
 203    surf[3] = pitch_bytes - 1;
 204
 205    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 206    if (surface->mt->mcs_mt) {
 207       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 208                                 is_render_target);
 209    }
 210
 211    surf[7] = surface->mt->fast_clear_color_value;
 212
 213    if (brw->is_haswell) {
 214       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 215                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 216                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 217                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 218    }
 219
 220    /* Emit relocation to surface contents */
 221    drm_intel_bo_emit_reloc(brw->batch.bo,
 222                            wm_surf_offset + 4,
 223                            mt->bo,
 224                            surf[1] - mt->bo->offset64,
 225                            read_domains, write_domain);
 226
 227    gen7_check_surface_setup(surf, is_render_target);
 228
 229    return wm_surf_offset;
 230 }
 231
 232
 233 /* 3DSTATE_VS
 234  *
 235  * Disable vertex shader.
 236  */
 237 static void
 238 gen7_blorp_emit_vs_disable(struct brw_context *brw)
 239 {
 240    BEGIN_BATCH(7);
 241    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 242    OUT_BATCH(0);
 243    OUT_BATCH(0);
 244    OUT_BATCH(0);
 245    OUT_BATCH(0);
 246    OUT_BATCH(0);
 247    OUT_BATCH(0);
 248    ADVANCE_BATCH();
 249
 250    BEGIN_BATCH(6);
 251    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 252    OUT_BATCH(0);
 253    OUT_BATCH(0);
 254    OUT_BATCH(0);
 255    OUT_BATCH(0);
 256    OUT_BATCH(0);
 257    ADVANCE_BATCH();
 258 }
 259
 260
 261 /* 3DSTATE_HS
 262  *
 263  * Disable the hull shader.
 264  */
 265 static void
 266 gen7_blorp_emit_hs_disable(struct brw_context *brw)
 267 {
 268    BEGIN_BATCH(7);
 269    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 270    OUT_BATCH(0);
 271    OUT_BATCH(0);
 272    OUT_BATCH(0);
 273    OUT_BATCH(0);
 274    OUT_BATCH(0);
 275    OUT_BATCH(0);
 276    ADVANCE_BATCH();
 277
 278    BEGIN_BATCH(7);
 279    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 280    OUT_BATCH(0);
 281    OUT_BATCH(0);
 282    OUT_BATCH(0);
 283    OUT_BATCH(0);
 284    OUT_BATCH(0);
 285    OUT_BATCH(0);
 286    ADVANCE_BATCH();
 287 }
 288
 289
 290 /* 3DSTATE_TE
 291  *
 292  * Disable the tesselation engine.
 293  */
 294 void
 295 gen7_blorp_emit_te_disable(struct brw_context *brw)
 296 {
 297    BEGIN_BATCH(4);
 298    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 299    OUT_BATCH(0);
 300    OUT_BATCH(0);
 301    OUT_BATCH(0);
 302    ADVANCE_BATCH();
 303 }
 304
 305
 306 /* 3DSTATE_DS
 307  *
 308  * Disable the domain shader.
 309  */
 310 static void
 311 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 312 {
 313    BEGIN_BATCH(7);
 314    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    OUT_BATCH(0);
 319    OUT_BATCH(0);
 320    OUT_BATCH(0);
 321    ADVANCE_BATCH();
 322
 323    BEGIN_BATCH(6);
 324    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 325    OUT_BATCH(0);
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    OUT_BATCH(0);
 330    ADVANCE_BATCH();
 331 }
 332
 333 /* 3DSTATE_GS
 334  *
 335  * Disable the geometry shader.
 336  */
 337 static void
 338 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 339 {
 340    BEGIN_BATCH(7);
 341    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 342    OUT_BATCH(0);
 343    OUT_BATCH(0);
 344    OUT_BATCH(0);
 345    OUT_BATCH(0);
 346    OUT_BATCH(0);
 347    OUT_BATCH(0);
 348    ADVANCE_BATCH();
 349
 350    /**
 351     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 352     * Geometry > Geometry Shader > State:
 353     *
 354     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 355     *     whole fixed function pipeline when the GS enable changes value in
 356     *     the 3DSTATE_GS."
 357     *
 358     * The hardware architects have clarified that in this context "flush the
 359     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 360     * Stall" bit set.
 361     */
 362    if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 363       gen7_emit_cs_stall_flush(brw);
 364
 365    BEGIN_BATCH(7);
 366    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 367    OUT_BATCH(0);
 368    OUT_BATCH(0);
 369    OUT_BATCH(0);
 370    OUT_BATCH(0);
 371    OUT_BATCH(0);
 372    OUT_BATCH(0);
 373    ADVANCE_BATCH();
 374    brw->gs.enabled = false;
 375 }
 376
 377 /* 3DSTATE_STREAMOUT
 378  *
 379  * Disable streamout.
 380  */
 381 static void
 382 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 383 {
 384    BEGIN_BATCH(3);
 385    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 386    OUT_BATCH(0);
 387    OUT_BATCH(0);
 388    ADVANCE_BATCH();
 389 }
 390
 391
 392 static void
 393 gen7_blorp_emit_sf_config(struct brw_context *brw,
 394                           const brw_blorp_params *params)
 395 {
 396    /* 3DSTATE_SF
 397     *
 398     * Disable ViewportTransformEnable (dw1.1)
 399     *
 400     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 401     * Primitives Overview":
 402     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 403     *     use of screen- space coordinates).
 404     *
 405     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 406     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 407     *
 408     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 409     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 410     *     SOLID: Any triangle or rectangle object found to be front-facing
 411     *     is rendered as a solid object. This setting is required when
 412     *     (rendering rectangle (RECTLIST) objects.
 413     */
 414    {
 415       BEGIN_BATCH(7);
 416       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 417       OUT_BATCH(params->depth_format <<
 418                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 419       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 420       OUT_BATCH(0);
 421       OUT_BATCH(0);
 422       OUT_BATCH(0);
 423       OUT_BATCH(0);
 424       ADVANCE_BATCH();
 425    }
 426
 427    /* 3DSTATE_SBE */
 428    {
 429       BEGIN_BATCH(14);
 430       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 431       OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
 432                 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 433                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 434                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 435                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 436       for (int i = 0; i < 12; ++i)
 437          OUT_BATCH(0);
 438       ADVANCE_BATCH();
 439    }
 440 }
 441
 442
 443 /**
 444  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 445  */
 446 static void
 447 gen7_blorp_emit_wm_config(struct brw_context *brw,
 448                           const brw_blorp_params *params,
 449                           brw_blorp_prog_data *prog_data)
 450 {
 451    uint32_t dw1 = 0, dw2 = 0;
 452
 453    switch (params->hiz_op) {
 454    case GEN6_HIZ_OP_DEPTH_CLEAR:
 455       dw1 |= GEN7_WM_DEPTH_CLEAR;
 456       break;
 457    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 458       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 459       break;
 460    case GEN6_HIZ_OP_HIZ_RESOLVE:
 461       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 462       break;
 463    case GEN6_HIZ_OP_NONE:
 464       break;
 465    default:
 466       unreachable("not reached");
 467    }
 468    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 469    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 470    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 471    if (params->use_wm_prog) {
 472       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 473       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 474    }
 475
 476       if (params->dst.num_samples > 1) {
 477          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 478          if (prog_data && prog_data->persample_msaa_dispatch)
 479             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 480          else
 481             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 482       } else {
 483          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 484          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 485       }
 486
 487    BEGIN_BATCH(3);
 488    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 489    OUT_BATCH(dw1);
 490    OUT_BATCH(dw2);
 491    ADVANCE_BATCH();
 492 }
 493
 494
 495 /**
 496  * 3DSTATE_PS
 497  *
 498  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 499  * that, thread dispatch info must still be specified.
 500  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 501  *       valid range for this field is [0x3, 0x2f].
 502  *     - A dispatch mode must be given; that is, at least one of the
 503  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 504  *       discovered through simulator error messages.
 505  */
 506 static void
 507 gen7_blorp_emit_ps_config(struct brw_context *brw,
 508                           const brw_blorp_params *params,
 509                           uint32_t prog_offset,
 510                           brw_blorp_prog_data *prog_data)
 511 {
 512    uint32_t dw2, dw4, dw5;
 513    const int max_threads_shift = brw->is_haswell ?
 514       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 515
 516    dw2 = dw4 = dw5 = 0;
 517    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 518
 519    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 520     * what the program is compiled for.  If there isn't, then it shouldn't
 521     * matter because no program is actually being run.  However, the hardware
 522     * gets angry if we don't enable at least one dispatch mode, so just enable
 523     * 16-pixel dispatch unconditionally.
 524     */
 525    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 526
 527    if (brw->is_haswell)
 528       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 529    if (params->use_wm_prog) {
 530       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 531       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 532       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 533    }
 534
 535    dw4 |= params->fast_clear_op;
 536
 537    BEGIN_BATCH(8);
 538    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 539    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 540    OUT_BATCH(dw2);
 541    OUT_BATCH(0);
 542    OUT_BATCH(dw4);
 543    OUT_BATCH(dw5);
 544    OUT_BATCH(0);
 545    OUT_BATCH(0);
 546    ADVANCE_BATCH();
 547 }
 548
 549
 550 void
 551 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 552                                           uint32_t wm_bind_bo_offset)
 553 {
 554    BEGIN_BATCH(2);
 555    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 556    OUT_BATCH(wm_bind_bo_offset);
 557    ADVANCE_BATCH();
 558 }
 559
 560
 561 void
 562 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 563                                           uint32_t sampler_offset)
 564 {
 565    BEGIN_BATCH(2);
 566    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 567    OUT_BATCH(sampler_offset);
 568    ADVANCE_BATCH();
 569 }
 570
 571
 572 void
 573 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 574                             uint32_t wm_push_const_offset)
 575 {
 576    const uint8_t mocs = GEN7_MOCS_L3;
 577
 578    /* Make sure the push constants fill an exact integer number of
 579     * registers.
 580     */
 581    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 582
 583    /* There must be at least one register worth of push constant data. */
 584    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 585
 586    /* Enable push constant buffer 0. */
 587    BEGIN_BATCH(7);
 588    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 589              (7 - 2));
 590    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 591    OUT_BATCH(0);
 592    OUT_BATCH(wm_push_const_offset | mocs);
 593    OUT_BATCH(0);
 594    OUT_BATCH(0);
 595    OUT_BATCH(0);
 596    ADVANCE_BATCH();
 597 }
 598
 599 void
 600 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 601 {
 602    BEGIN_BATCH(7);
 603    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 604    OUT_BATCH(0);
 605    OUT_BATCH(0);
 606    OUT_BATCH(0);
 607    OUT_BATCH(0);
 608    OUT_BATCH(0);
 609    OUT_BATCH(0);
 610    ADVANCE_BATCH();
 611 }
 612
 613 static void
 614 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 615                                      const brw_blorp_params *params)
 616 {
 617    const uint8_t mocs = GEN7_MOCS_L3;
 618    uint32_t surfwidth, surfheight;
 619    uint32_t surftype;
 620    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 621    unsigned int min_array_element;
 622    GLenum gl_target = params->depth.mt->target;
 623    unsigned int lod;
 624
 625    switch (gl_target) {
 626    case GL_TEXTURE_CUBE_MAP_ARRAY:
 627    case GL_TEXTURE_CUBE_MAP:
 628       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 629        * situation, but experiments show that gl_Layer doesn't work when we do
 630        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 631        * equivalent.
 632        */
 633       surftype = BRW_SURFACE_2D;
 634       depth *= 6;
 635       break;
 636    default:
 637       surftype = translate_tex_target(gl_target);
 638       break;
 639    }
 640
 641    min_array_element = params->depth.layer;
 642    if (params->depth.mt->num_samples > 1) {
 643       /* Convert physical layer to logical layer. */
 644       min_array_element /= params->depth.mt->num_samples;
 645    }
 646
 647    lod = params->depth.level - params->depth.mt->first_level;
 648
 649    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 650       /* HIZ ops for lod 0 may set the width & height a little
 651        * larger to allow the fast depth clear to fit the hardware
 652        * alignment requirements. (8x4)
 653        */
 654       surfwidth = params->depth.width;
 655       surfheight = params->depth.height;
 656    } else {
 657       surfwidth = params->depth.mt->logical_width0;
 658       surfheight = params->depth.mt->logical_height0;
 659    }
 660
 661    /* 3DSTATE_DEPTH_BUFFER */
 662    {
 663       brw_emit_depth_stall_flushes(brw);
 664
 665       BEGIN_BATCH(7);
 666       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 667       OUT_BATCH((params->depth.mt->pitch - 1) |
 668                 params->depth_format << 18 |
 669                 1 << 22 | /* hiz enable */
 670                 1 << 28 | /* depth write */
 671                 surftype << 29);
 672       OUT_RELOC(params->depth.mt->bo,
 673                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 674                 0);
 675       OUT_BATCH((surfwidth - 1) << 4 |
 676                 (surfheight - 1) << 18 |
 677                 lod);
 678       OUT_BATCH(((depth - 1) << 21) |
 679                 (min_array_element << 10) |
 680                 mocs);
 681       OUT_BATCH(0);
 682       OUT_BATCH((depth - 1) << 21);
 683       ADVANCE_BATCH();
 684    }
 685
 686    /* 3DSTATE_HIER_DEPTH_BUFFER */
 687    {
 688       struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 689
 690       BEGIN_BATCH(3);
 691       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 692       OUT_BATCH((mocs << 25) |
 693                 (hiz_buf->pitch - 1));
 694       OUT_RELOC(hiz_buf->bo,
 695                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 696                 0);
 697       ADVANCE_BATCH();
 698    }
 699
 700    /* 3DSTATE_STENCIL_BUFFER */
 701    {
 702       BEGIN_BATCH(3);
 703       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 704       OUT_BATCH(0);
 705       OUT_BATCH(0);
 706       ADVANCE_BATCH();
 707    }
 708 }
 709
 710
 711 static void
 712 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 713 {
 714    brw_emit_depth_stall_flushes(brw);
 715
 716    BEGIN_BATCH(7);
 717    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 718    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 719    OUT_BATCH(0);
 720    OUT_BATCH(0);
 721    OUT_BATCH(0);
 722    OUT_BATCH(0);
 723    OUT_BATCH(0);
 724    ADVANCE_BATCH();
 725
 726    BEGIN_BATCH(3);
 727    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 728    OUT_BATCH(0);
 729    OUT_BATCH(0);
 730    ADVANCE_BATCH();
 731
 732    BEGIN_BATCH(3);
 733    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 734    OUT_BATCH(0);
 735    OUT_BATCH(0);
 736    ADVANCE_BATCH();
 737 }
 738
 739
 740 /* 3DSTATE_CLEAR_PARAMS
 741  *
 742  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 743  * 3DSTATE_CLEAR_PARAMS:
 744  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 745  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 746  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 747  */
 748 void
 749 gen7_blorp_emit_clear_params(struct brw_context *brw,
 750                              const brw_blorp_params *params)
 751 {
 752    BEGIN_BATCH(3);
 753    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 754    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 755    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 756    ADVANCE_BATCH();
 757 }
 758
 759
 760 /* 3DPRIMITIVE */
 761 void
 762 gen7_blorp_emit_primitive(struct brw_context *brw,
 763                           const brw_blorp_params *params)
 764 {
 765    BEGIN_BATCH(7);
 766    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 767    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 768              _3DPRIM_RECTLIST);
 769    OUT_BATCH(3); /* vertex count per instance */
 770    OUT_BATCH(0);
 771    OUT_BATCH(params->num_layers); /* instance count */
 772    OUT_BATCH(0);
 773    OUT_BATCH(0);
 774    ADVANCE_BATCH();
 775 }
 776
 777
 778 /**
 779  * \copydoc gen6_blorp_exec()
 780  */
 781 void
 782 gen7_blorp_exec(struct brw_context *brw,
 783                 const brw_blorp_params *params)
 784 {
 785    if (brw->gen >= 8)
 786       return;
 787
 788    brw_blorp_prog_data *prog_data = NULL;
 789    uint32_t cc_blend_state_offset = 0;
 790    uint32_t cc_state_offset = 0;
 791    uint32_t depthstencil_offset;
 792    uint32_t wm_push_const_offset = 0;
 793    uint32_t wm_bind_bo_offset = 0;
 794    uint32_t sampler_offset = 0;
 795
 796    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 797    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 798    gen6_emit_3dstate_sample_mask(brw,
 799                                  params->dst.num_samples > 1 ?
 800                                  (1 << params->dst.num_samples) - 1 : 1);
 801    gen6_blorp_emit_state_base_address(brw, params);
 802    gen6_blorp_emit_vertices(brw, params);
 803    gen7_blorp_emit_urb_config(brw);
 804    if (params->use_wm_prog) {
 805       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 806       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 807       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 808       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 809    }
 810    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 811    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 812    if (brw->use_resource_streamer)
 813       gen7_disable_hw_binding_tables(brw);
 814    if (params->use_wm_prog) {
 815       uint32_t wm_surf_offset_renderbuffer;
 816       uint32_t wm_surf_offset_texture = 0;
 817       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 818       intel_miptree_used_for_rendering(params->dst.mt);
 819       wm_surf_offset_renderbuffer =
 820          gen7_blorp_emit_surface_state(brw, &params->dst,
 821                                        I915_GEM_DOMAIN_RENDER,
 822                                        I915_GEM_DOMAIN_RENDER,
 823                                        true /* is_render_target */);
 824       if (params->src.mt) {
 825          wm_surf_offset_texture =
 826             gen7_blorp_emit_surface_state(brw, &params->src,
 827                                           I915_GEM_DOMAIN_SAMPLER, 0,
 828                                           false /* is_render_target */);
 829       }
 830       wm_bind_bo_offset =
 831          gen6_blorp_emit_binding_table(brw,
 832                                        wm_surf_offset_renderbuffer,
 833                                        wm_surf_offset_texture);
 834       sampler_offset =
 835          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 836    }
 837    gen7_blorp_emit_vs_disable(brw);
 838    gen7_blorp_emit_hs_disable(brw);
 839    gen7_blorp_emit_te_disable(brw);
 840    gen7_blorp_emit_ds_disable(brw);
 841    gen7_blorp_emit_gs_disable(brw);
 842    gen7_blorp_emit_streamout_disable(brw);
 843    gen6_blorp_emit_clip_disable(brw);
 844    gen7_blorp_emit_sf_config(brw, params);
 845    gen7_blorp_emit_wm_config(brw, params, prog_data);
 846    if (params->use_wm_prog) {
 847       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 848       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 849       gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
 850    } else {
 851       gen7_blorp_emit_constant_ps_disable(brw);
 852    }
 853    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 854    gen7_blorp_emit_cc_viewport(brw);
 855
 856    if (params->depth.mt)
 857       gen7_blorp_emit_depth_stencil_config(brw, params);
 858    else
 859       gen7_blorp_emit_depth_disable(brw);
 860    gen7_blorp_emit_clear_params(brw, params);
 861    gen6_blorp_emit_drawing_rectangle(brw, params);
 862    gen7_blorp_emit_primitive(brw, params);
 863 }