src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  44  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  45  *
  46  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  47  *     programmed in order for the programming of this state to be
  48  *     valid.
  49  */
  50 static void
  51 gen7_blorp_emit_urb_config(struct brw_context *brw,
  52                            const brw_blorp_params *params)
  53 {
  54    /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
  55     * 1.15:0 "VS Number of URB Entries".
  56     */
  57    gen7_emit_urb_state(brw,
  58                        32 /* num_vs_entries */,
  59                        2 /* vs_size */,
  60                        2 /* vs_start */,
  61                        0 /* num_gs_entries */,
  62                        1 /* gs_size */,
  63                        2 /* gs_start */);
  64 }
  65
  66
  67 /* 3DSTATE_BLEND_STATE_POINTERS */
  68 static void
  69 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  70                                     const brw_blorp_params *params,
  71                                     uint32_t cc_blend_state_offset)
  72 {
  73    BEGIN_BATCH(2);
  74    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  75    OUT_BATCH(cc_blend_state_offset | 1);
  76    ADVANCE_BATCH();
  77 }
  78
  79
  80 /* 3DSTATE_CC_STATE_POINTERS */
  81 static void
  82 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  83                                  const brw_blorp_params *params,
  84                                  uint32_t cc_state_offset)
  85 {
  86    BEGIN_BATCH(2);
  87    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  88    OUT_BATCH(cc_state_offset | 1);
  89    ADVANCE_BATCH();
  90 }
  91
  92 static void
  93 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  94                             const brw_blorp_params *params)
  95 {
  96    struct brw_cc_viewport *ccv;
  97    uint32_t cc_vp_offset;
  98
  99    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 100                                                    sizeof(*ccv), 32,
 101                                                    &cc_vp_offset);
 102    ccv->min_depth = 0.0;
 103    ccv->max_depth = 1.0;
 104
 105    BEGIN_BATCH(2);
 106    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 107    OUT_BATCH(cc_vp_offset);
 108    ADVANCE_BATCH();
 109 }
 110
 111
 112 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 113  *
 114  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 115  */
 116 static void
 117 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 118                                              const brw_blorp_params *params,
 119                                              uint32_t depthstencil_offset)
 120 {
 121    BEGIN_BATCH(2);
 122    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 123    OUT_BATCH(depthstencil_offset | 1);
 124    ADVANCE_BATCH();
 125 }
 126
 127
 128 /* SURFACE_STATE for renderbuffer or texture surface (see
 129  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 130  */
 131 static uint32_t
 132 gen7_blorp_emit_surface_state(struct brw_context *brw,
 133                               const brw_blorp_params *params,
 134                               const brw_blorp_surface_info *surface,
 135                               uint32_t read_domains, uint32_t write_domain,
 136                               bool is_render_target)
 137 {
 138    uint32_t wm_surf_offset;
 139    uint32_t width = surface->width;
 140    uint32_t height = surface->height;
 141    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 142     * color surfaces, width and height are measured in pixels; we don't need
 143     * to divide them by 2 as we do for Gen6 (see
 144     * gen6_blorp_emit_surface_state).
 145     */
 146    struct intel_region *region = surface->mt->region;
 147    uint32_t tile_x, tile_y;
 148    const uint8_t mocs = GEN7_MOCS_L3;
 149
 150    uint32_t tiling = surface->map_stencil_as_y_tiled
 151       ? I915_TILING_Y : region->tiling;
 152
 153    uint32_t *surf = (uint32_t *)
 154       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 155    memset(surf, 0, 8 * 4);
 156
 157    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 158              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 159              gen7_surface_tiling_mode(tiling);
 160
 161    if (surface->mt->align_h == 4)
 162       surf[0] |= GEN7_SURFACE_VALIGN_4;
 163    if (surface->mt->align_w == 8)
 164       surf[0] |= GEN7_SURFACE_HALIGN_8;
 165
 166    if (surface->array_spacing_lod0)
 167       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 168    else
 169       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 170
 171    /* reloc */
 172    surf[1] =
 173       surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
 174
 175    /* Note that the low bits of these fields are missing, so
 176     * there's the possibility of getting in trouble.
 177     */
 178    assert(tile_x % 4 == 0);
 179    assert(tile_y % 2 == 0);
 180    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 181              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 182              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 183
 184    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 185              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 186
 187    uint32_t pitch_bytes = region->pitch;
 188    if (surface->map_stencil_as_y_tiled)
 189       pitch_bytes *= 2;
 190    surf[3] = pitch_bytes - 1;
 191
 192    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 193    if (surface->mt->mcs_mt) {
 194       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 195                                 is_render_target);
 196    }
 197
 198    surf[7] = surface->mt->fast_clear_color_value;
 199
 200    if (brw->is_haswell) {
 201       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 202                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 203                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 204                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 205    }
 206
 207    /* Emit relocation to surface contents */
 208    drm_intel_bo_emit_reloc(brw->batch.bo,
 209                            wm_surf_offset + 4,
 210                            region->bo,
 211                            surf[1] - region->bo->offset,
 212                            read_domains, write_domain);
 213
 214    gen7_check_surface_setup(surf, is_render_target);
 215
 216    return wm_surf_offset;
 217 }
 218
 219
 220 /**
 221  * SAMPLER_STATE.  See gen7_update_sampler_state().
 222  */
 223 static uint32_t
 224 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 225                               const brw_blorp_params *params)
 226 {
 227    uint32_t sampler_offset;
 228
 229    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 230       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 231                       sizeof(struct gen7_sampler_state),
 232                       32, &sampler_offset);
 233    memset(sampler, 0, sizeof(*sampler));
 234
 235    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 236    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 237    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 238
 239    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 240    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 241    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 242
 243    //   sampler->ss0.min_mag_neq = 1;
 244
 245    /* Set LOD bias:
 246     */
 247    sampler->ss0.lod_bias = 0;
 248
 249    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 250    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 251
 252    /* Set BaseMipLevel, MaxLOD, MinLOD:
 253     *
 254     * XXX: I don't think that using firstLevel, lastLevel works,
 255     * because we always setup the surface state as if firstLevel ==
 256     * level zero.  Probably have to subtract firstLevel from each of
 257     * these:
 258     */
 259    sampler->ss0.base_level = U_FIXED(0, 1);
 260
 261    sampler->ss1.max_lod = U_FIXED(0, 8);
 262    sampler->ss1.min_lod = U_FIXED(0, 8);
 263
 264    sampler->ss3.non_normalized_coord = 1;
 265
 266    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 267       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 268       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 269    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 270       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 271       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 272
 273    return sampler_offset;
 274 }
 275
 276
 277 /* 3DSTATE_VS
 278  *
 279  * Disable vertex shader.
 280  */
 281 static void
 282 gen7_blorp_emit_vs_disable(struct brw_context *brw,
 283                            const brw_blorp_params *params)
 284 {
 285    BEGIN_BATCH(7);
 286    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    OUT_BATCH(0);
 290    OUT_BATCH(0);
 291    OUT_BATCH(0);
 292    OUT_BATCH(0);
 293    ADVANCE_BATCH();
 294
 295    BEGIN_BATCH(6);
 296    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    OUT_BATCH(0);
 300    OUT_BATCH(0);
 301    OUT_BATCH(0);
 302    ADVANCE_BATCH();
 303 }
 304
 305
 306 /* 3DSTATE_HS
 307  *
 308  * Disable the hull shader.
 309  */
 310 static void
 311 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 312                            const brw_blorp_params *params)
 313 {
 314    BEGIN_BATCH(7);
 315    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318    OUT_BATCH(0);
 319    OUT_BATCH(0);
 320    OUT_BATCH(0);
 321    OUT_BATCH(0);
 322    ADVANCE_BATCH();
 323
 324    BEGIN_BATCH(7);
 325    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    OUT_BATCH(0);
 330    OUT_BATCH(0);
 331    OUT_BATCH(0);
 332    ADVANCE_BATCH();
 333 }
 334
 335
 336 /* 3DSTATE_TE
 337  *
 338  * Disable the tesselation engine.
 339  */
 340 static void
 341 gen7_blorp_emit_te_disable(struct brw_context *brw,
 342                            const brw_blorp_params *params)
 343 {
 344    BEGIN_BATCH(4);
 345    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 346    OUT_BATCH(0);
 347    OUT_BATCH(0);
 348    OUT_BATCH(0);
 349    ADVANCE_BATCH();
 350 }
 351
 352
 353 /* 3DSTATE_DS
 354  *
 355  * Disable the domain shader.
 356  */
 357 static void
 358 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 359                            const brw_blorp_params *params)
 360 {
 361    BEGIN_BATCH(7);
 362    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 363    OUT_BATCH(0);
 364    OUT_BATCH(0);
 365    OUT_BATCH(0);
 366    OUT_BATCH(0);
 367    OUT_BATCH(0);
 368    OUT_BATCH(0);
 369    ADVANCE_BATCH();
 370
 371    BEGIN_BATCH(6);
 372    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 373    OUT_BATCH(0);
 374    OUT_BATCH(0);
 375    OUT_BATCH(0);
 376    OUT_BATCH(0);
 377    OUT_BATCH(0);
 378    ADVANCE_BATCH();
 379 }
 380
 381 /* 3DSTATE_GS
 382  *
 383  * Disable the geometry shader.
 384  */
 385 static void
 386 gen7_blorp_emit_gs_disable(struct brw_context *brw,
 387                            const brw_blorp_params *params)
 388 {
 389    BEGIN_BATCH(7);
 390    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 391    OUT_BATCH(0);
 392    OUT_BATCH(0);
 393    OUT_BATCH(0);
 394    OUT_BATCH(0);
 395    OUT_BATCH(0);
 396    OUT_BATCH(0);
 397    ADVANCE_BATCH();
 398
 399    BEGIN_BATCH(7);
 400    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 401    OUT_BATCH(0);
 402    OUT_BATCH(0);
 403    OUT_BATCH(0);
 404    OUT_BATCH(0);
 405    OUT_BATCH(0);
 406    OUT_BATCH(0);
 407    ADVANCE_BATCH();
 408 }
 409
 410 /* 3DSTATE_STREAMOUT
 411  *
 412  * Disable streamout.
 413  */
 414 static void
 415 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 416                                   const brw_blorp_params *params)
 417 {
 418    BEGIN_BATCH(3);
 419    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 420    OUT_BATCH(0);
 421    OUT_BATCH(0);
 422    ADVANCE_BATCH();
 423 }
 424
 425
 426 static void
 427 gen7_blorp_emit_sf_config(struct brw_context *brw,
 428                           const brw_blorp_params *params)
 429 {
 430    /* 3DSTATE_SF
 431     *
 432     * Disable ViewportTransformEnable (dw1.1)
 433     *
 434     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 435     * Primitives Overview":
 436     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 437     *     use of screen- space coordinates).
 438     *
 439     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 440     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 441     *
 442     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 443     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 444     *     SOLID: Any triangle or rectangle object found to be front-facing
 445     *     is rendered as a solid object. This setting is required when
 446     *     (rendering rectangle (RECTLIST) objects.
 447     */
 448    {
 449       BEGIN_BATCH(7);
 450       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 451       OUT_BATCH(params->depth_format <<
 452                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 453       OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 454       OUT_BATCH(0);
 455       OUT_BATCH(0);
 456       OUT_BATCH(0);
 457       OUT_BATCH(0);
 458       ADVANCE_BATCH();
 459    }
 460
 461    /* 3DSTATE_SBE */
 462    {
 463       BEGIN_BATCH(14);
 464       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 465       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 466                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 467                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 468       for (int i = 0; i < 12; ++i)
 469          OUT_BATCH(0);
 470       ADVANCE_BATCH();
 471    }
 472 }
 473
 474
 475 /**
 476  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 477  */
 478 static void
 479 gen7_blorp_emit_wm_config(struct brw_context *brw,
 480                           const brw_blorp_params *params,
 481                           brw_blorp_prog_data *prog_data)
 482 {
 483    uint32_t dw1 = 0, dw2 = 0;
 484
 485    switch (params->hiz_op) {
 486    case GEN6_HIZ_OP_DEPTH_CLEAR:
 487       dw1 |= GEN7_WM_DEPTH_CLEAR;
 488       break;
 489    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 490       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 491       break;
 492    case GEN6_HIZ_OP_HIZ_RESOLVE:
 493       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 494       break;
 495    case GEN6_HIZ_OP_NONE:
 496       break;
 497    default:
 498       assert(0);
 499       break;
 500    }
 501    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 502    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 503    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 504    if (params->use_wm_prog) {
 505       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 506       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 507    }
 508
 509       if (params->num_samples > 1) {
 510          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 511          if (prog_data && prog_data->persample_msaa_dispatch)
 512             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 513          else
 514             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 515       } else {
 516          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 517          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 518       }
 519
 520    BEGIN_BATCH(3);
 521    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 522    OUT_BATCH(dw1);
 523    OUT_BATCH(dw2);
 524    ADVANCE_BATCH();
 525 }
 526
 527
 528 /**
 529  * 3DSTATE_PS
 530  *
 531  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 532  * that, thread dispatch info must still be specified.
 533  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 534  *       valid range for this field is [0x3, 0x2f].
 535  *     - A dispatch mode must be given; that is, at least one of the
 536  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 537  *       discovered through simulator error messages.
 538  */
 539 static void
 540 gen7_blorp_emit_ps_config(struct brw_context *brw,
 541                           const brw_blorp_params *params,
 542                           uint32_t prog_offset,
 543                           brw_blorp_prog_data *prog_data)
 544 {
 545    uint32_t dw2, dw4, dw5;
 546    const int max_threads_shift = brw->is_haswell ?
 547       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 548
 549    dw2 = dw4 = dw5 = 0;
 550    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 551
 552    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 553     * what the program is compiled for.  If there isn't, then it shouldn't
 554     * matter because no program is actually being run.  However, the hardware
 555     * gets angry if we don't enable at least one dispatch mode, so just enable
 556     * 16-pixel dispatch unconditionally.
 557     */
 558    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 559
 560    if (brw->is_haswell)
 561       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 562    if (params->use_wm_prog) {
 563       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 564       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 565       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 566    }
 567
 568    switch (params->fast_clear_op) {
 569    case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
 570       dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 571       break;
 572    case GEN7_FAST_CLEAR_OP_RESOLVE:
 573       dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
 574       break;
 575    default:
 576       break;
 577    }
 578
 579    BEGIN_BATCH(8);
 580    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 581    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 582    OUT_BATCH(dw2);
 583    OUT_BATCH(0);
 584    OUT_BATCH(dw4);
 585    OUT_BATCH(dw5);
 586    OUT_BATCH(0);
 587    OUT_BATCH(0);
 588    ADVANCE_BATCH();
 589 }
 590
 591
 592 static void
 593 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 594                                           const brw_blorp_params *params,
 595                                           uint32_t wm_bind_bo_offset)
 596 {
 597    BEGIN_BATCH(2);
 598    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 599    OUT_BATCH(wm_bind_bo_offset);
 600    ADVANCE_BATCH();
 601 }
 602
 603
 604 static void
 605 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 606                                           const brw_blorp_params *params,
 607                                           uint32_t sampler_offset)
 608 {
 609    BEGIN_BATCH(2);
 610    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 611    OUT_BATCH(sampler_offset);
 612    ADVANCE_BATCH();
 613 }
 614
 615
 616 static void
 617 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 618                             const brw_blorp_params *params,
 619                             uint32_t wm_push_const_offset)
 620 {
 621    const uint8_t mocs = GEN7_MOCS_L3;
 622
 623    /* Make sure the push constants fill an exact integer number of
 624     * registers.
 625     */
 626    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 627
 628    /* There must be at least one register worth of push constant data. */
 629    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 630
 631    /* Enable push constant buffer 0. */
 632    BEGIN_BATCH(7);
 633    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 634              (7 - 2));
 635    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 636    OUT_BATCH(0);
 637    OUT_BATCH(wm_push_const_offset | mocs);
 638    OUT_BATCH(0);
 639    OUT_BATCH(0);
 640    OUT_BATCH(0);
 641    ADVANCE_BATCH();
 642 }
 643
 644 static void
 645 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
 646                                     const brw_blorp_params *params)
 647 {
 648    BEGIN_BATCH(7);
 649    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 650    OUT_BATCH(0);
 651    OUT_BATCH(0);
 652    OUT_BATCH(0);
 653    OUT_BATCH(0);
 654    OUT_BATCH(0);
 655    OUT_BATCH(0);
 656    ADVANCE_BATCH();
 657 }
 658
 659 static void
 660 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 661                                      const brw_blorp_params *params)
 662 {
 663    const uint8_t mocs = GEN7_MOCS_L3;
 664    uint32_t surfwidth, surfheight;
 665    uint32_t surftype;
 666    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 667    unsigned int min_array_element;
 668    GLenum gl_target = params->depth.mt->target;
 669    unsigned int lod;
 670
 671    switch (gl_target) {
 672    case GL_TEXTURE_CUBE_MAP_ARRAY:
 673    case GL_TEXTURE_CUBE_MAP:
 674       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 675        * situation, but experiments show that gl_Layer doesn't work when we do
 676        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 677        * equivalent.
 678        */
 679       surftype = BRW_SURFACE_2D;
 680       depth *= 6;
 681       break;
 682    default:
 683       surftype = translate_tex_target(gl_target);
 684       break;
 685    }
 686
 687    min_array_element = params->depth.layer;
 688    if (params->depth.mt->num_samples > 1) {
 689       /* Convert physical layer to logical layer. */
 690       min_array_element /= params->depth.mt->num_samples;
 691    }
 692
 693    lod = params->depth.level - params->depth.mt->first_level;
 694
 695    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 696       /* HIZ ops for lod 0 may set the width & height a little
 697        * larger to allow the fast depth clear to fit the hardware
 698        * alignment requirements. (8x4)
 699        */
 700       surfwidth = params->depth.width;
 701       surfheight = params->depth.height;
 702    } else {
 703       surfwidth = params->depth.mt->physical_width0;
 704       surfheight = params->depth.mt->physical_height0;
 705    }
 706
 707    /* 3DSTATE_DEPTH_BUFFER */
 708    {
 709       intel_emit_depth_stall_flushes(brw);
 710
 711       BEGIN_BATCH(7);
 712       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 713       OUT_BATCH((params->depth.mt->region->pitch - 1) |
 714                 params->depth_format << 18 |
 715                 1 << 22 | /* hiz enable */
 716                 1 << 28 | /* depth write */
 717                 surftype << 29);
 718       OUT_RELOC(params->depth.mt->region->bo,
 719                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 720                 0);
 721       OUT_BATCH((surfwidth - 1) << 4 |
 722                 (surfheight - 1) << 18 |
 723                 lod);
 724       OUT_BATCH(((depth - 1) << 21) |
 725                 (min_array_element << 10) |
 726                 mocs);
 727       OUT_BATCH(0);
 728       OUT_BATCH((depth - 1) << 21);
 729       ADVANCE_BATCH();
 730    }
 731
 732    /* 3DSTATE_HIER_DEPTH_BUFFER */
 733    {
 734       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 735
 736       BEGIN_BATCH(3);
 737       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 738       OUT_BATCH((mocs << 25) |
 739                 (hiz_region->pitch - 1));
 740       OUT_RELOC(hiz_region->bo,
 741                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 742                 0);
 743       ADVANCE_BATCH();
 744    }
 745
 746    /* 3DSTATE_STENCIL_BUFFER */
 747    {
 748       BEGIN_BATCH(3);
 749       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 750       OUT_BATCH(0);
 751       OUT_BATCH(0);
 752       ADVANCE_BATCH();
 753    }
 754 }
 755
 756
 757 static void
 758 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 759                               const brw_blorp_params *params)
 760 {
 761    intel_emit_depth_stall_flushes(brw);
 762
 763    BEGIN_BATCH(7);
 764    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 765    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 766    OUT_BATCH(0);
 767    OUT_BATCH(0);
 768    OUT_BATCH(0);
 769    OUT_BATCH(0);
 770    OUT_BATCH(0);
 771    ADVANCE_BATCH();
 772 }
 773
 774
 775 /* 3DSTATE_CLEAR_PARAMS
 776  *
 777  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 778  * 3DSTATE_CLEAR_PARAMS:
 779  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 780  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 781  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 782  */
 783 static void
 784 gen7_blorp_emit_clear_params(struct brw_context *brw,
 785                              const brw_blorp_params *params)
 786 {
 787    BEGIN_BATCH(3);
 788    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 789    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 790    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 791    ADVANCE_BATCH();
 792 }
 793
 794
 795 /* 3DPRIMITIVE */
 796 static void
 797 gen7_blorp_emit_primitive(struct brw_context *brw,
 798                           const brw_blorp_params *params)
 799 {
 800    BEGIN_BATCH(7);
 801    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 802    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 803              _3DPRIM_RECTLIST);
 804    OUT_BATCH(3); /* vertex count per instance */
 805    OUT_BATCH(0);
 806    OUT_BATCH(1); /* instance count */
 807    OUT_BATCH(0);
 808    OUT_BATCH(0);
 809    ADVANCE_BATCH();
 810 }
 811
 812
 813 /**
 814  * \copydoc gen6_blorp_exec()
 815  */
 816 void
 817 gen7_blorp_exec(struct brw_context *brw,
 818                 const brw_blorp_params *params)
 819 {
 820    brw_blorp_prog_data *prog_data = NULL;
 821    uint32_t cc_blend_state_offset = 0;
 822    uint32_t cc_state_offset = 0;
 823    uint32_t depthstencil_offset;
 824    uint32_t wm_push_const_offset = 0;
 825    uint32_t wm_bind_bo_offset = 0;
 826    uint32_t sampler_offset = 0;
 827
 828    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 829    gen6_blorp_emit_batch_head(brw, params);
 830    gen6_emit_3dstate_multisample(brw, params->num_samples);
 831    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
 832    gen6_blorp_emit_state_base_address(brw, params);
 833    gen6_blorp_emit_vertices(brw, params);
 834    gen7_blorp_emit_urb_config(brw, params);
 835    if (params->use_wm_prog) {
 836       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 837       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 838       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 839       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 840    }
 841    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 842    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 843                                                 depthstencil_offset);
 844    if (params->use_wm_prog) {
 845       uint32_t wm_surf_offset_renderbuffer;
 846       uint32_t wm_surf_offset_texture = 0;
 847       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 848       intel_miptree_used_for_rendering(params->dst.mt);
 849       wm_surf_offset_renderbuffer =
 850          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 851                                        I915_GEM_DOMAIN_RENDER,
 852                                        I915_GEM_DOMAIN_RENDER,
 853                                        true /* is_render_target */);
 854       if (params->src.mt) {
 855          wm_surf_offset_texture =
 856             gen7_blorp_emit_surface_state(brw, params, &params->src,
 857                                           I915_GEM_DOMAIN_SAMPLER, 0,
 858                                           false /* is_render_target */);
 859       }
 860       wm_bind_bo_offset =
 861          gen6_blorp_emit_binding_table(brw, params,
 862                                        wm_surf_offset_renderbuffer,
 863                                        wm_surf_offset_texture);
 864       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 865    }
 866    gen7_blorp_emit_vs_disable(brw, params);
 867    gen7_blorp_emit_hs_disable(brw, params);
 868    gen7_blorp_emit_te_disable(brw, params);
 869    gen7_blorp_emit_ds_disable(brw, params);
 870    gen7_blorp_emit_gs_disable(brw, params);
 871    gen7_blorp_emit_streamout_disable(brw, params);
 872    gen6_blorp_emit_clip_disable(brw, params);
 873    gen7_blorp_emit_sf_config(brw, params);
 874    gen7_blorp_emit_wm_config(brw, params, prog_data);
 875    if (params->use_wm_prog) {
 876       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 877                                                 wm_bind_bo_offset);
 878       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 879       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 880    } else {
 881       gen7_blorp_emit_constant_ps_disable(brw, params);
 882    }
 883    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 884    gen7_blorp_emit_cc_viewport(brw, params);
 885
 886    if (params->depth.mt)
 887       gen7_blorp_emit_depth_stencil_config(brw, params);
 888    else
 889       gen7_blorp_emit_depth_disable(brw, params);
 890    gen7_blorp_emit_clear_params(brw, params);
 891    gen6_blorp_emit_drawing_rectangle(brw, params);
 892    gen7_blorp_emit_primitive(brw, params);
 893 }