src/mesa/drivers/dri/i965/gen7_cs_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "brw_context.h"
  26 #include "brw_cs.h"
  27 #include "brw_eu.h"
  28 #include "brw_wm.h"
  29 #include "brw_shader.h"
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "brw_state.h"
  33 #include "program/prog_statevars.h"
  34 #include "compiler/glsl/ir_uniform.h"
  35
  36 static void
  37 brw_upload_cs_state(struct brw_context *brw)
  38 {
  39    if (!brw->cs.prog_data)
  40       return;
  41
  42    uint32_t offset;
  43    uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  44                                                 8 * 4, 64, &offset);
  45    struct brw_stage_state *stage_state = &brw->cs.base;
  46    struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
  47    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
  48    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
  49
  50    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  51       brw->vtbl.emit_buffer_surface_state(
  52          brw, &stage_state->surf_offset[
  53                  prog_data->binding_table.shader_time_start],
  54          brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
  55          brw->shader_time.bo->size, 1, true);
  56    }
  57
  58    uint32_t *bind = (uint32_t*) brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  59                                             prog_data->binding_table.size_bytes,
  60                                             32, &stage_state->bind_bo_offset);
  61
  62    uint32_t dwords = brw->gen < 8 ? 8 : 9;
  63    BEGIN_BATCH(dwords);
  64    OUT_BATCH(MEDIA_VFE_STATE << 16 | (dwords - 2));
  65
  66    if (prog_data->total_scratch) {
  67       if (brw->gen >= 8) {
  68          /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
  69           * where 0 = 1k, 1 = 4k, 2 = 8k, ..., 11 = 2M.
  70           */
  71          OUT_RELOC64(stage_state->scratch_bo,
  72                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  73                      ffs(prog_data->total_scratch) - 11);
  74       } else if (brw->is_haswell) {
  75          /* Haswell's Per Thread Scratch Space is in the range [0, 10]
  76           * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
  77           */
  78          OUT_RELOC(stage_state->scratch_bo,
  79                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  80                    ffs(prog_data->total_scratch) - 12);
  81       } else {
  82          /* This is wrong but we'll fix it later */
  83          OUT_RELOC(stage_state->scratch_bo,
  84                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  85                    ffs(prog_data->total_scratch) - 11);
  86       }
  87    } else {
  88       OUT_BATCH(0);
  89       if (brw->gen >= 8)
  90          OUT_BATCH(0);
  91    }
  92
  93    const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0;
  94    const uint32_t vfe_gpgpu_mode =
  95       brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0;
  96    OUT_BATCH(SET_FIELD(brw->max_cs_threads - 1, MEDIA_VFE_STATE_MAX_THREADS) |
  97              SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) |
  98              SET_FIELD(1, MEDIA_VFE_STATE_RESET_GTW_TIMER) |
  99              SET_FIELD(1, MEDIA_VFE_STATE_BYPASS_GTW) |
 100              vfe_gpgpu_mode);
 101
 102    OUT_BATCH(0);
 103    const uint32_t vfe_urb_allocation = brw->gen >= 8 ? 2 : 0;
 104
 105    /* We are uploading duplicated copies of push constant uniforms for each
 106     * thread. Although the local id data needs to vary per thread, it won't
 107     * change for other uniform data. Unfortunately this duplication is
 108     * required for gen7. As of Haswell, this duplication can be avoided, but
 109     * this older mechanism with duplicated data continues to work.
 110     *
 111     * FINISHME: As of Haswell, we could make use of the
 112     * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length" field
 113     * to only store one copy of uniform data.
 114     *
 115     * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
 116     * which is described in the GPGPU_WALKER command and in the Broadwell PRM
 117     * Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
 118     * Operations => GPGPU Mode => Indirect Payload Storage.
 119     *
 120     * Note: The constant data is built in brw_upload_cs_push_constants below.
 121     */
 122    const uint32_t vfe_curbe_allocation =
 123       ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
 124             cs_prog_data->push.cross_thread.regs, 2);
 125    OUT_BATCH(SET_FIELD(vfe_urb_allocation, MEDIA_VFE_STATE_URB_ALLOC) |
 126              SET_FIELD(vfe_curbe_allocation, MEDIA_VFE_STATE_CURBE_ALLOC));
 127    OUT_BATCH(0);
 128    OUT_BATCH(0);
 129    OUT_BATCH(0);
 130    ADVANCE_BATCH();
 131
 132    if (cs_prog_data->push.total.size > 0) {
 133       BEGIN_BATCH(4);
 134       OUT_BATCH(MEDIA_CURBE_LOAD << 16 | (4 - 2));
 135       OUT_BATCH(0);
 136       OUT_BATCH(ALIGN(cs_prog_data->push.total.size, 64));
 137       OUT_BATCH(stage_state->push_const_offset);
 138       ADVANCE_BATCH();
 139    }
 140
 141    /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
 142    memcpy(bind, stage_state->surf_offset,
 143           prog_data->binding_table.size_bytes);
 144
 145    memset(desc, 0, 8 * 4);
 146
 147    int dw = 0;
 148    desc[dw++] = brw->cs.base.prog_offset;
 149    if (brw->gen >= 8)
 150       desc[dw++] = 0; /* Kernel Start Pointer High */
 151    desc[dw++] = 0;
 152    desc[dw++] = stage_state->sampler_offset |
 153       ((stage_state->sampler_count + 3) / 4);
 154    desc[dw++] = stage_state->bind_bo_offset;
 155    desc[dw++] = SET_FIELD(cs_prog_data->push.per_thread.regs,
 156                           MEDIA_CURBE_READ_LENGTH);
 157    const uint32_t media_threads =
 158       brw->gen >= 8 ?
 159       SET_FIELD(cs_prog_data->threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
 160       SET_FIELD(cs_prog_data->threads, MEDIA_GPGPU_THREAD_COUNT);
 161    assert(cs_prog_data->threads <= brw->max_cs_threads);
 162
 163    const uint32_t slm_size = encode_slm_size(devinfo, prog_data->total_shared);
 164
 165    desc[dw++] =
 166       SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
 167       SET_FIELD(slm_size, MEDIA_SHARED_LOCAL_MEMORY_SIZE) |
 168       media_threads;
 169
 170    desc[dw++] =
 171       SET_FIELD(cs_prog_data->push.cross_thread.regs, CROSS_THREAD_READ_LENGTH);
 172
 173    BEGIN_BATCH(4);
 174    OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD << 16 | (4 - 2));
 175    OUT_BATCH(0);
 176    OUT_BATCH(8 * 4);
 177    OUT_BATCH(offset);
 178    ADVANCE_BATCH();
 179 }
 180
 181 const struct brw_tracked_state brw_cs_state = {
 182    .dirty = {
 183       .mesa = _NEW_PROGRAM_CONSTANTS,
 184       .brw = BRW_NEW_BATCH |
 185              BRW_NEW_BLORP |
 186              BRW_NEW_CS_PROG_DATA |
 187              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 188              BRW_NEW_SAMPLER_STATE_TABLE |
 189              BRW_NEW_SURFACES,
 190    },
 191    .emit = brw_upload_cs_state
 192 };
 193
 194
 195 /**
 196  * Creates a region containing the push constants for the CS on gen7+.
 197  *
 198  * Push constants are constant values (such as GLSL uniforms) that are
 199  * pre-loaded into a shader stage's register space at thread spawn time.
 200  *
 201  * For other stages, see brw_curbe.c:brw_upload_constant_buffer for the
 202  * equivalent gen4/5 code and gen6_vs_state.c:gen6_upload_push_constants for
 203  * gen6+.
 204  */
 205 static void
 206 brw_upload_cs_push_constants(struct brw_context *brw,
 207                              const struct gl_program *prog,
 208                              const struct brw_cs_prog_data *cs_prog_data,
 209                              struct brw_stage_state *stage_state,
 210                              enum aub_state_struct_type type)
 211 {
 212    struct gl_context *ctx = &brw->ctx;
 213    const struct brw_stage_prog_data *prog_data =
 214       (struct brw_stage_prog_data*) cs_prog_data;
 215
 216    /* Updates the ParamaterValues[i] pointers for all parameters of the
 217     * basic type of PROGRAM_STATE_VAR.
 218     */
 219    /* XXX: Should this happen somewhere before to get our state flag set? */
 220    _mesa_load_state_parameters(ctx, prog->Parameters);
 221
 222    if (cs_prog_data->push.total.size == 0) {
 223       stage_state->push_const_size = 0;
 224       return;
 225    }
 226
 227
 228    gl_constant_value *param = (gl_constant_value*)
 229       brw_state_batch(brw, type, ALIGN(cs_prog_data->push.total.size, 64),
 230                       64, &stage_state->push_const_offset);
 231    assert(param);
 232
 233    STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 234
 235    if (cs_prog_data->push.cross_thread.size > 0) {
 236       gl_constant_value *param_copy = param;
 237       assert(cs_prog_data->thread_local_id_index < 0 ||
 238              cs_prog_data->thread_local_id_index >=
 239                 cs_prog_data->push.cross_thread.dwords);
 240       for (unsigned i = 0;
 241            i < cs_prog_data->push.cross_thread.dwords;
 242            i++) {
 243          param_copy[i] = *prog_data->param[i];
 244       }
 245    }
 246
 247    gl_constant_value thread_id;
 248    if (cs_prog_data->push.per_thread.size > 0) {
 249       for (unsigned t = 0; t < cs_prog_data->threads; t++) {
 250          unsigned dst =
 251             8 * (cs_prog_data->push.per_thread.regs * t +
 252                  cs_prog_data->push.cross_thread.regs);
 253          unsigned src = cs_prog_data->push.cross_thread.dwords;
 254          for ( ; src < prog_data->nr_params; src++, dst++) {
 255             if (src != cs_prog_data->thread_local_id_index)
 256                param[dst] = *prog_data->param[src];
 257             else {
 258                thread_id.u = t * cs_prog_data->simd_size;
 259                param[dst] = thread_id;
 260             }
 261          }
 262       }
 263    }
 264
 265    stage_state->push_const_size =
 266       cs_prog_data->push.cross_thread.regs +
 267       cs_prog_data->push.per_thread.regs;
 268 }
 269
 270
 271 static void
 272 gen7_upload_cs_push_constants(struct brw_context *brw)
 273 {
 274    struct brw_stage_state *stage_state = &brw->cs.base;
 275
 276    /* BRW_NEW_COMPUTE_PROGRAM */
 277    const struct brw_compute_program *cp =
 278       (struct brw_compute_program *) brw->compute_program;
 279
 280    if (cp) {
 281       /* CACHE_NEW_CS_PROG */
 282       struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
 283
 284       brw_upload_cs_push_constants(brw, &cp->program.Base, cs_prog_data,
 285                                    stage_state, AUB_TRACE_WM_CONSTANTS);
 286    }
 287 }
 288
 289 const struct brw_tracked_state gen7_cs_push_constants = {
 290    .dirty = {
 291       .mesa = _NEW_PROGRAM_CONSTANTS,
 292       .brw = BRW_NEW_BATCH |
 293              BRW_NEW_BLORP |
 294              BRW_NEW_COMPUTE_PROGRAM |
 295              BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 296    },
 297    .emit = gen7_upload_cs_push_constants,
 298 };
 299
 300 /**
 301  * Creates a new CS constant buffer reflecting the current CS program's
 302  * constants, if needed by the CS program.
 303  */
 304 static void
 305 brw_upload_cs_pull_constants(struct brw_context *brw)
 306 {
 307    struct brw_stage_state *stage_state = &brw->cs.base;
 308
 309    /* BRW_NEW_COMPUTE_PROGRAM */
 310    struct brw_compute_program *cp =
 311       (struct brw_compute_program *) brw->compute_program;
 312
 313    /* BRW_NEW_CS_PROG_DATA */
 314    const struct brw_stage_prog_data *prog_data = &brw->cs.prog_data->base;
 315
 316    /* _NEW_PROGRAM_CONSTANTS */
 317    brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &cp->program.Base,
 318                              stage_state, prog_data);
 319 }
 320
 321 const struct brw_tracked_state brw_cs_pull_constants = {
 322    .dirty = {
 323       .mesa = _NEW_PROGRAM_CONSTANTS,
 324       .brw = BRW_NEW_BATCH |
 325              BRW_NEW_BLORP |
 326              BRW_NEW_COMPUTE_PROGRAM |
 327              BRW_NEW_CS_PROG_DATA,
 328    },
 329    .emit = brw_upload_cs_pull_constants,
 330 };