src/mesa/drivers/dri/i965/gen7_cs_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "brw_context.h"
  26 #include "brw_cs.h"
  27 #include "brw_eu.h"
  28 #include "brw_wm.h"
  29 #include "brw_shader.h"
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "brw_state.h"
  33
  34 static unsigned
  35 get_cs_thread_count(const struct brw_cs_prog_data *cs_prog_data)
  36 {
  37    const unsigned simd_size = cs_prog_data->simd_size;
  38    unsigned group_size = cs_prog_data->local_size[0] *
  39       cs_prog_data->local_size[1] * cs_prog_data->local_size[2];
  40
  41    return (group_size + simd_size - 1) / simd_size;
  42 }
  43
  44
  45 static void
  46 brw_upload_cs_state(struct brw_context *brw)
  47 {
  48    if (!brw->cs.prog_data)
  49       return;
  50
  51    uint32_t offset;
  52    uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  53                                                 8 * 4, 64, &offset);
  54    struct gl_program *prog = (struct gl_program *) brw->compute_program;
  55    struct brw_stage_state *stage_state = &brw->cs.base;
  56    struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
  57    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
  58
  59    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  60       brw->vtbl.emit_buffer_surface_state(
  61          brw, &stage_state->surf_offset[
  62                  prog_data->binding_table.shader_time_start],
  63          brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
  64          brw->shader_time.bo->size, 1, true);
  65    }
  66
  67    uint32_t *bind = (uint32_t*) brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  68                                             prog_data->binding_table.size_bytes,
  69                                             32, &stage_state->bind_bo_offset);
  70
  71    unsigned local_id_dwords = 0;
  72
  73    if (prog->SystemValuesRead & SYSTEM_BIT_LOCAL_INVOCATION_ID)
  74       local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
  75
  76    unsigned push_constant_data_size =
  77       (prog_data->nr_params + local_id_dwords) * sizeof(gl_constant_value);
  78    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
  79    unsigned push_constant_regs = reg_aligned_constant_size / 32;
  80    unsigned threads = get_cs_thread_count(cs_prog_data);
  81
  82    uint32_t dwords = brw->gen < 8 ? 8 : 9;
  83    BEGIN_BATCH(dwords);
  84    OUT_BATCH(MEDIA_VFE_STATE << 16 | (dwords - 2));
  85
  86    if (prog_data->total_scratch) {
  87       if (brw->gen >= 8)
  88          OUT_RELOC64(stage_state->scratch_bo,
  89                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  90                      ffs(prog_data->total_scratch) - 11);
  91       else
  92          OUT_RELOC(stage_state->scratch_bo,
  93                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  94                    ffs(prog_data->total_scratch) - 11);
  95    } else {
  96       OUT_BATCH(0);
  97       if (brw->gen >= 8)
  98          OUT_BATCH(0);
  99    }
 100
 101    const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0;
 102    const uint32_t vfe_gpgpu_mode =
 103       brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0;
 104    OUT_BATCH(SET_FIELD(brw->max_cs_threads - 1, MEDIA_VFE_STATE_MAX_THREADS) |
 105              SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) |
 106              SET_FIELD(1, MEDIA_VFE_STATE_RESET_GTW_TIMER) |
 107              SET_FIELD(1, MEDIA_VFE_STATE_BYPASS_GTW) |
 108              vfe_gpgpu_mode);
 109
 110    OUT_BATCH(0);
 111    const uint32_t vfe_urb_allocation = brw->gen >= 8 ? 2 : 0;
 112
 113    /* We are uploading duplicated copies of push constant uniforms for each
 114     * thread. Although the local id data needs to vary per thread, it won't
 115     * change for other uniform data. Unfortunately this duplication is
 116     * required for gen7. As of Haswell, this duplication can be avoided, but
 117     * this older mechanism with duplicated data continues to work.
 118     *
 119     * FINISHME: As of Haswell, we could make use of the
 120     * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length" field
 121     * to only store one copy of uniform data.
 122     *
 123     * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
 124     * which is described in the GPGPU_WALKER command and in the Broadwell PRM
 125     * Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
 126     * Operations => GPGPU Mode => Indirect Payload Storage.
 127     *
 128     * Note: The constant data is built in brw_upload_cs_push_constants below.
 129     */
 130    const uint32_t vfe_curbe_allocation = push_constant_regs * threads;
 131    OUT_BATCH(SET_FIELD(vfe_urb_allocation, MEDIA_VFE_STATE_URB_ALLOC) |
 132              SET_FIELD(vfe_curbe_allocation, MEDIA_VFE_STATE_CURBE_ALLOC));
 133    OUT_BATCH(0);
 134    OUT_BATCH(0);
 135    OUT_BATCH(0);
 136    ADVANCE_BATCH();
 137
 138    if (reg_aligned_constant_size > 0) {
 139       BEGIN_BATCH(4);
 140       OUT_BATCH(MEDIA_CURBE_LOAD << 16 | (4 - 2));
 141       OUT_BATCH(0);
 142       OUT_BATCH(reg_aligned_constant_size * threads);
 143       OUT_BATCH(stage_state->push_const_offset);
 144       ADVANCE_BATCH();
 145    }
 146
 147    /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
 148    memcpy(bind, stage_state->surf_offset,
 149           prog_data->binding_table.size_bytes);
 150
 151    memset(desc, 0, 8 * 4);
 152
 153    int dw = 0;
 154    desc[dw++] = brw->cs.base.prog_offset;
 155    if (brw->gen >= 8)
 156       desc[dw++] = 0; /* Kernel Start Pointer High */
 157    desc[dw++] = 0;
 158    desc[dw++] = stage_state->sampler_offset |
 159       ((stage_state->sampler_count + 3) / 4);
 160    desc[dw++] = stage_state->bind_bo_offset;
 161    desc[dw++] = SET_FIELD(push_constant_regs, MEDIA_CURBE_READ_LENGTH);
 162    const uint32_t media_threads =
 163       brw->gen >= 8 ?
 164       SET_FIELD(threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
 165       SET_FIELD(threads, MEDIA_GPGPU_THREAD_COUNT);
 166    assert(threads <= brw->max_cs_threads);
 167    desc[dw++] =
 168       SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
 169       media_threads;
 170
 171    BEGIN_BATCH(4);
 172    OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD << 16 | (4 - 2));
 173    OUT_BATCH(0);
 174    OUT_BATCH(8 * 4);
 175    OUT_BATCH(offset);
 176    ADVANCE_BATCH();
 177 }
 178
 179 const struct brw_tracked_state brw_cs_state = {
 180    .dirty = {
 181       .mesa = _NEW_PROGRAM_CONSTANTS,
 182       .brw = BRW_NEW_BATCH |
 183              BRW_NEW_CS_PROG_DATA |
 184              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 185              BRW_NEW_SURFACES,
 186    },
 187    .emit = brw_upload_cs_state
 188 };
 189
 190
 191 /**
 192  * Creates a region containing the push constants for the CS on gen7+.
 193  *
 194  * Push constants are constant values (such as GLSL uniforms) that are
 195  * pre-loaded into a shader stage's register space at thread spawn time.
 196  *
 197  * For other stages, see brw_curbe.c:brw_upload_constant_buffer for the
 198  * equivalent gen4/5 code and gen6_vs_state.c:gen6_upload_push_constants for
 199  * gen6+.
 200  */
 201 static void
 202 brw_upload_cs_push_constants(struct brw_context *brw,
 203                              const struct gl_program *prog,
 204                              const struct brw_cs_prog_data *cs_prog_data,
 205                              struct brw_stage_state *stage_state,
 206                              enum aub_state_struct_type type)
 207 {
 208    struct gl_context *ctx = &brw->ctx;
 209    const struct brw_stage_prog_data *prog_data =
 210       (struct brw_stage_prog_data*) cs_prog_data;
 211    unsigned local_id_dwords = 0;
 212
 213    if (prog->SystemValuesRead & SYSTEM_BIT_LOCAL_INVOCATION_ID)
 214       local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 215
 216    /* Updates the ParamaterValues[i] pointers for all parameters of the
 217     * basic type of PROGRAM_STATE_VAR.
 218     */
 219    /* XXX: Should this happen somewhere before to get our state flag set? */
 220    _mesa_load_state_parameters(ctx, prog->Parameters);
 221
 222    if (prog_data->nr_params == 0 && local_id_dwords == 0) {
 223       stage_state->push_const_size = 0;
 224    } else {
 225       gl_constant_value *param;
 226       unsigned i, t;
 227
 228       const unsigned push_constant_data_size =
 229          (local_id_dwords + prog_data->nr_params) * sizeof(gl_constant_value);
 230       const unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 231       const unsigned param_aligned_count =
 232          reg_aligned_constant_size / sizeof(*param);
 233
 234       unsigned threads = get_cs_thread_count(cs_prog_data);
 235
 236       param = (gl_constant_value*)
 237          brw_state_batch(brw, type,
 238                          reg_aligned_constant_size * threads,
 239                          32, &stage_state->push_const_offset);
 240       assert(param);
 241
 242       STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 243
 244       brw_cs_fill_local_id_payload(cs_prog_data, param, threads,
 245                                    reg_aligned_constant_size);
 246
 247       /* _NEW_PROGRAM_CONSTANTS */
 248       for (t = 0; t < threads; t++) {
 249          gl_constant_value *next_param =
 250             &param[t * param_aligned_count + local_id_dwords];
 251          for (i = 0; i < prog_data->nr_params; i++) {
 252             next_param[i] = *prog_data->param[i];
 253          }
 254       }
 255
 256       stage_state->push_const_size = ALIGN(prog_data->nr_params, 8) / 8;
 257    }
 258 }
 259
 260
 261 static void
 262 gen7_upload_cs_push_constants(struct brw_context *brw)
 263 {
 264    struct brw_stage_state *stage_state = &brw->cs.base;
 265
 266    /* BRW_NEW_COMPUTE_PROGRAM */
 267    const struct brw_compute_program *cp =
 268       (struct brw_compute_program *) brw->compute_program;
 269
 270    if (cp) {
 271       /* CACHE_NEW_CS_PROG */
 272       struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
 273
 274       brw_upload_cs_push_constants(brw, &cp->program.Base, cs_prog_data,
 275                                    stage_state, AUB_TRACE_WM_CONSTANTS);
 276    }
 277 }
 278
 279 const struct brw_tracked_state gen7_cs_push_constants = {
 280    .dirty = {
 281       .mesa = _NEW_PROGRAM_CONSTANTS,
 282       .brw = BRW_NEW_BATCH |
 283              BRW_NEW_COMPUTE_PROGRAM |
 284              BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 285    },
 286    .emit = gen7_upload_cs_push_constants,
 287 };