src/mesa/drivers/dri/i965/gen7_cs_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "brw_context.h"
  26 #include "brw_defines.h"
  27 #include "brw_cs.h"
  28 #include "brw_wm.h"
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "brw_state.h"
  32 #include "program/prog_statevars.h"
  33 #include "compiler/glsl/ir_uniform.h"
  34 #include "main/shaderapi.h"
  35
  36 static void
  37 brw_upload_cs_state(struct brw_context *brw)
  38 {
  39    if (!brw->cs.base.prog_data)
  40       return;
  41
  42    uint32_t offset;
  43    uint32_t *desc = (uint32_t*) brw_state_batch(brw, 8 * 4, 64, &offset);
  44    struct brw_stage_state *stage_state = &brw->cs.base;
  45    struct brw_stage_prog_data *prog_data = stage_state->prog_data;
  46    struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
  47    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  48
  49    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  50       brw_emit_buffer_surface_state(
  51          brw, &stage_state->surf_offset[
  52                  prog_data->binding_table.shader_time_start],
  53          brw->shader_time.bo, 0, ISL_FORMAT_RAW,
  54          brw->shader_time.bo->size, 1, true);
  55    }
  56
  57    uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
  58                                     32, &stage_state->bind_bo_offset);
  59
  60    uint32_t dwords = brw->gen < 8 ? 8 : 9;
  61    BEGIN_BATCH(dwords);
  62    OUT_BATCH(MEDIA_VFE_STATE << 16 | (dwords - 2));
  63
  64    if (prog_data->total_scratch) {
  65       if (brw->gen >= 8) {
  66          /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
  67           * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
  68           */
  69          OUT_RELOC64(stage_state->scratch_bo,
  70                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  71                      ffs(stage_state->per_thread_scratch) - 11);
  72       } else if (brw->is_haswell) {
  73          /* Haswell's Per Thread Scratch Space is in the range [0, 10]
  74           * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
  75           */
  76          OUT_RELOC(stage_state->scratch_bo,
  77                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  78                    ffs(stage_state->per_thread_scratch) - 12);
  79       } else {
  80          /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
  81           * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
  82           */
  83          OUT_RELOC(stage_state->scratch_bo,
  84                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  85                    stage_state->per_thread_scratch / 1024 - 1);
  86       }
  87    } else {
  88       OUT_BATCH(0);
  89       if (brw->gen >= 8)
  90          OUT_BATCH(0);
  91    }
  92
  93    const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0;
  94    const uint32_t vfe_gpgpu_mode =
  95       brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0;
  96    const uint32_t subslices = MAX2(brw->screen->subslice_total, 1);
  97    OUT_BATCH(SET_FIELD(devinfo->max_cs_threads * subslices - 1,
  98                        MEDIA_VFE_STATE_MAX_THREADS) |
  99              SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) |
 100              SET_FIELD(1, MEDIA_VFE_STATE_RESET_GTW_TIMER) |
 101              SET_FIELD(1, MEDIA_VFE_STATE_BYPASS_GTW) |
 102              vfe_gpgpu_mode);
 103
 104    OUT_BATCH(0);
 105    const uint32_t vfe_urb_allocation = brw->gen >= 8 ? 2 : 0;
 106
 107    /* We are uploading duplicated copies of push constant uniforms for each
 108     * thread. Although the local id data needs to vary per thread, it won't
 109     * change for other uniform data. Unfortunately this duplication is
 110     * required for gen7. As of Haswell, this duplication can be avoided, but
 111     * this older mechanism with duplicated data continues to work.
 112     *
 113     * FINISHME: As of Haswell, we could make use of the
 114     * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length" field
 115     * to only store one copy of uniform data.
 116     *
 117     * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
 118     * which is described in the GPGPU_WALKER command and in the Broadwell PRM
 119     * Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
 120     * Operations => GPGPU Mode => Indirect Payload Storage.
 121     *
 122     * Note: The constant data is built in brw_upload_cs_push_constants below.
 123     */
 124    const uint32_t vfe_curbe_allocation =
 125       ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
 126             cs_prog_data->push.cross_thread.regs, 2);
 127    OUT_BATCH(SET_FIELD(vfe_urb_allocation, MEDIA_VFE_STATE_URB_ALLOC) |
 128              SET_FIELD(vfe_curbe_allocation, MEDIA_VFE_STATE_CURBE_ALLOC));
 129    OUT_BATCH(0);
 130    OUT_BATCH(0);
 131    OUT_BATCH(0);
 132    ADVANCE_BATCH();
 133
 134    if (cs_prog_data->push.total.size > 0) {
 135       BEGIN_BATCH(4);
 136       OUT_BATCH(MEDIA_CURBE_LOAD << 16 | (4 - 2));
 137       OUT_BATCH(0);
 138       OUT_BATCH(ALIGN(cs_prog_data->push.total.size, 64));
 139       OUT_BATCH(stage_state->push_const_offset);
 140       ADVANCE_BATCH();
 141    }
 142
 143    /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
 144    memcpy(bind, stage_state->surf_offset,
 145           prog_data->binding_table.size_bytes);
 146
 147    memset(desc, 0, 8 * 4);
 148
 149    int dw = 0;
 150    desc[dw++] = brw->cs.base.prog_offset;
 151    if (brw->gen >= 8)
 152       desc[dw++] = 0; /* Kernel Start Pointer High */
 153    desc[dw++] = 0;
 154    desc[dw++] = stage_state->sampler_offset |
 155       ((stage_state->sampler_count + 3) / 4);
 156    desc[dw++] = stage_state->bind_bo_offset;
 157    desc[dw++] = SET_FIELD(cs_prog_data->push.per_thread.regs,
 158                           MEDIA_CURBE_READ_LENGTH);
 159    const uint32_t media_threads =
 160       brw->gen >= 8 ?
 161       SET_FIELD(cs_prog_data->threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
 162       SET_FIELD(cs_prog_data->threads, MEDIA_GPGPU_THREAD_COUNT);
 163    assert(cs_prog_data->threads <= devinfo->max_cs_threads);
 164
 165    const uint32_t slm_size =
 166       encode_slm_size(devinfo->gen, prog_data->total_shared);
 167
 168    desc[dw++] =
 169       SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
 170       SET_FIELD(slm_size, MEDIA_SHARED_LOCAL_MEMORY_SIZE) |
 171       media_threads;
 172
 173    desc[dw++] =
 174       SET_FIELD(cs_prog_data->push.cross_thread.regs, CROSS_THREAD_READ_LENGTH);
 175
 176    BEGIN_BATCH(4);
 177    OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD << 16 | (4 - 2));
 178    OUT_BATCH(0);
 179    OUT_BATCH(8 * 4);
 180    OUT_BATCH(offset);
 181    ADVANCE_BATCH();
 182 }
 183
 184 const struct brw_tracked_state brw_cs_state = {
 185    .dirty = {
 186       .mesa = _NEW_PROGRAM_CONSTANTS,
 187       .brw = BRW_NEW_BATCH |
 188              BRW_NEW_BLORP |
 189              BRW_NEW_CS_PROG_DATA |
 190              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 191              BRW_NEW_SAMPLER_STATE_TABLE |
 192              BRW_NEW_SURFACES,
 193    },
 194    .emit = brw_upload_cs_state
 195 };
 196
 197
 198 /**
 199  * Creates a region containing the push constants for the CS on gen7+.
 200  *
 201  * Push constants are constant values (such as GLSL uniforms) that are
 202  * pre-loaded into a shader stage's register space at thread spawn time.
 203  *
 204  * For other stages, see brw_curbe.c:brw_upload_constant_buffer for the
 205  * equivalent gen4/5 code and gen6_vs_state.c:gen6_upload_push_constants for
 206  * gen6+.
 207  */
 208 static void
 209 brw_upload_cs_push_constants(struct brw_context *brw,
 210                              const struct gl_program *prog,
 211                              const struct brw_cs_prog_data *cs_prog_data,
 212                              struct brw_stage_state *stage_state)
 213 {
 214    struct gl_context *ctx = &brw->ctx;
 215    const struct brw_stage_prog_data *prog_data =
 216       (struct brw_stage_prog_data*) cs_prog_data;
 217
 218    /* Updates the ParamaterValues[i] pointers for all parameters of the
 219     * basic type of PROGRAM_STATE_VAR.
 220     */
 221    /* XXX: Should this happen somewhere before to get our state flag set? */
 222    _mesa_load_state_parameters(ctx, prog->Parameters);
 223
 224    if (cs_prog_data->push.total.size == 0) {
 225       stage_state->push_const_size = 0;
 226       return;
 227    }
 228
 229
 230    gl_constant_value *param = (gl_constant_value*)
 231       brw_state_batch(brw, ALIGN(cs_prog_data->push.total.size, 64),
 232                       64, &stage_state->push_const_offset);
 233    assert(param);
 234
 235    STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 236
 237    if (cs_prog_data->push.cross_thread.size > 0) {
 238       gl_constant_value *param_copy = param;
 239       assert(cs_prog_data->thread_local_id_index < 0 ||
 240              cs_prog_data->thread_local_id_index >=
 241                 cs_prog_data->push.cross_thread.dwords);
 242       for (unsigned i = 0;
 243            i < cs_prog_data->push.cross_thread.dwords;
 244            i++) {
 245          param_copy[i] = *prog_data->param[i];
 246       }
 247    }
 248
 249    gl_constant_value thread_id;
 250    if (cs_prog_data->push.per_thread.size > 0) {
 251       for (unsigned t = 0; t < cs_prog_data->threads; t++) {
 252          unsigned dst =
 253             8 * (cs_prog_data->push.per_thread.regs * t +
 254                  cs_prog_data->push.cross_thread.regs);
 255          unsigned src = cs_prog_data->push.cross_thread.dwords;
 256          for ( ; src < prog_data->nr_params; src++, dst++) {
 257             if (src != cs_prog_data->thread_local_id_index)
 258                param[dst] = *prog_data->param[src];
 259             else {
 260                thread_id.u = t * cs_prog_data->simd_size;
 261                param[dst] = thread_id;
 262             }
 263          }
 264       }
 265    }
 266
 267    stage_state->push_const_size =
 268       cs_prog_data->push.cross_thread.regs +
 269       cs_prog_data->push.per_thread.regs;
 270 }
 271
 272
 273 static void
 274 gen7_upload_cs_push_constants(struct brw_context *brw)
 275 {
 276    struct brw_stage_state *stage_state = &brw->cs.base;
 277
 278    /* BRW_NEW_COMPUTE_PROGRAM */
 279    const struct brw_program *cp = (struct brw_program *) brw->compute_program;
 280
 281    if (cp) {
 282       /* BRW_NEW_CS_PROG_DATA */
 283       struct brw_cs_prog_data *cs_prog_data =
 284          brw_cs_prog_data(brw->cs.base.prog_data);
 285
 286       _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
 287       brw_upload_cs_push_constants(brw, &cp->program, cs_prog_data,
 288                                    stage_state);
 289    }
 290 }
 291
 292 const struct brw_tracked_state gen7_cs_push_constants = {
 293    .dirty = {
 294       .mesa = _NEW_PROGRAM_CONSTANTS,
 295       .brw = BRW_NEW_BATCH |
 296              BRW_NEW_BLORP |
 297              BRW_NEW_COMPUTE_PROGRAM |
 298              BRW_NEW_CS_PROG_DATA |
 299              BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 300    },
 301    .emit = gen7_upload_cs_push_constants,
 302 };
 303
 304 /**
 305  * Creates a new CS constant buffer reflecting the current CS program's
 306  * constants, if needed by the CS program.
 307  */
 308 static void
 309 brw_upload_cs_pull_constants(struct brw_context *brw)
 310 {
 311    struct brw_stage_state *stage_state = &brw->cs.base;
 312
 313    /* BRW_NEW_COMPUTE_PROGRAM */
 314    struct brw_program *cp = (struct brw_program *) brw->compute_program;
 315
 316    /* BRW_NEW_CS_PROG_DATA */
 317    const struct brw_stage_prog_data *prog_data = brw->cs.base.prog_data;
 318
 319    _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
 320    /* _NEW_PROGRAM_CONSTANTS */
 321    brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &cp->program,
 322                              stage_state, prog_data);
 323 }
 324
 325 const struct brw_tracked_state brw_cs_pull_constants = {
 326    .dirty = {
 327       .mesa = _NEW_PROGRAM_CONSTANTS,
 328       .brw = BRW_NEW_BATCH |
 329              BRW_NEW_BLORP |
 330              BRW_NEW_COMPUTE_PROGRAM |
 331              BRW_NEW_CS_PROG_DATA,
 332    },
 333    .emit = brw_upload_cs_pull_constants,
 334 };