src/mesa/drivers/dri/i965/gen7_disable.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29 static void
  30 disable_stages(struct brw_context *brw)
  31 {
  32    /* Disable the HS Unit */
  33    BEGIN_BATCH(7);
  34    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
  35    OUT_BATCH(0);
  36    OUT_BATCH(0);
  37    OUT_BATCH(0);
  38    OUT_BATCH(0);
  39    OUT_BATCH(0);
  40    OUT_BATCH(0);
  41    ADVANCE_BATCH();
  42
  43    BEGIN_BATCH(7);
  44    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  45    OUT_BATCH(0);
  46    OUT_BATCH(0);
  47    OUT_BATCH(0);
  48    OUT_BATCH(0);
  49    OUT_BATCH(0);
  50    OUT_BATCH(0);
  51    ADVANCE_BATCH();
  52
  53    BEGIN_BATCH(2);
  54    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
  55    OUT_BATCH(brw->hw_bt_pool.next_offset);
  56    ADVANCE_BATCH();
  57
  58    /* Disable the TE */
  59    BEGIN_BATCH(4);
  60    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
  61    OUT_BATCH(0);
  62    OUT_BATCH(0);
  63    OUT_BATCH(0);
  64    ADVANCE_BATCH();
  65
  66    /* Disable the DS Unit */
  67    BEGIN_BATCH(7);
  68    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
  69    OUT_BATCH(0);
  70    OUT_BATCH(0);
  71    OUT_BATCH(0);
  72    OUT_BATCH(0);
  73    OUT_BATCH(0);
  74    OUT_BATCH(0);
  75    ADVANCE_BATCH();
  76
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
  79    OUT_BATCH(0);
  80    OUT_BATCH(0);
  81    OUT_BATCH(0);
  82    OUT_BATCH(0);
  83    OUT_BATCH(0);
  84    ADVANCE_BATCH();
  85
  86    BEGIN_BATCH(2);
  87    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
  88    OUT_BATCH(brw->hw_bt_pool.next_offset);
  89    ADVANCE_BATCH();
  90 }
  91
  92 const struct brw_tracked_state gen7_disable_stages = {
  93    .dirty = {
  94       .mesa  = 0,
  95       .brw   = BRW_NEW_CONTEXT,
  96    },
  97    .emit = disable_stages,
  98 };