i965/fs: Add support for translating ir_triop_fma into MAD.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_disable.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "intel_batchbuffer.h"
28
29 static void
30 disable_stages(struct brw_context *brw)
31 {
32 assert(!brw->gs.prog_active);
33
34 /* Disable the Geometry Shader (GS) Unit */
35 BEGIN_BATCH(7);
36 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
37 OUT_BATCH(0);
38 OUT_BATCH(0);
39 OUT_BATCH(0);
40 OUT_BATCH(0);
41 OUT_BATCH(0);
42 OUT_BATCH(0);
43 ADVANCE_BATCH();
44
45 BEGIN_BATCH(7);
46 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
47 OUT_BATCH(0); /* prog_bo */
48 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
49 (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
50 OUT_BATCH(0); /* scratch space base offset */
51 OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
52 (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
53 GEN7_GS_INCLUDE_VERTEX_HANDLES |
54 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
55 OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
56 GEN6_GS_STATISTICS_ENABLE);
57 OUT_BATCH(0);
58 ADVANCE_BATCH();
59
60 BEGIN_BATCH(2);
61 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
62 OUT_BATCH(0);
63 ADVANCE_BATCH();
64
65 /* Disable the HS Unit */
66 BEGIN_BATCH(7);
67 OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
68 OUT_BATCH(0);
69 OUT_BATCH(0);
70 OUT_BATCH(0);
71 OUT_BATCH(0);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 ADVANCE_BATCH();
75
76 BEGIN_BATCH(7);
77 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
78 OUT_BATCH(0);
79 OUT_BATCH(0);
80 OUT_BATCH(0);
81 OUT_BATCH(0);
82 OUT_BATCH(0);
83 OUT_BATCH(0);
84 ADVANCE_BATCH();
85
86 BEGIN_BATCH(2);
87 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
88 OUT_BATCH(0);
89 ADVANCE_BATCH();
90
91 /* Disable the TE */
92 BEGIN_BATCH(4);
93 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
94 OUT_BATCH(0);
95 OUT_BATCH(0);
96 OUT_BATCH(0);
97 ADVANCE_BATCH();
98
99 /* Disable the DS Unit */
100 BEGIN_BATCH(7);
101 OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
102 OUT_BATCH(0);
103 OUT_BATCH(0);
104 OUT_BATCH(0);
105 OUT_BATCH(0);
106 OUT_BATCH(0);
107 OUT_BATCH(0);
108 ADVANCE_BATCH();
109
110 BEGIN_BATCH(6);
111 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
112 OUT_BATCH(0);
113 OUT_BATCH(0);
114 OUT_BATCH(0);
115 OUT_BATCH(0);
116 OUT_BATCH(0);
117 ADVANCE_BATCH();
118
119 BEGIN_BATCH(2);
120 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
121 OUT_BATCH(0);
122 ADVANCE_BATCH();
123 }
124
125 const struct brw_tracked_state gen7_disable_stages = {
126 .dirty = {
127 .mesa = 0,
128 .brw = BRW_NEW_CONTEXT,
129 .cache = 0,
130 },
131 .emit = disable_stages,
132 };