src/mesa/drivers/dri/i965/gen7_ds_state.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29 static void
  30 gen7_upload_tes_push_constants(struct brw_context *brw)
  31 {
  32    struct brw_stage_state *stage_state = &brw->tes.base;
  33    /* BRW_NEW_TESS_PROGRAMS */
  34    const struct brw_tess_eval_program *tep =
  35       (struct brw_tess_eval_program *) brw->tess_eval_program;
  36
  37    if (tep) {
  38       /* BRW_NEW_TES_PROG_DATA */
  39       const struct brw_stage_prog_data *prog_data = &brw->tes.prog_data->base.base;
  40       gen6_upload_push_constants(brw, &tep->program.Base, prog_data,
  41                                       stage_state, AUB_TRACE_VS_CONSTANTS);
  42    }
  43
  44    gen7_upload_constant_state(brw, stage_state, tep, _3DSTATE_CONSTANT_DS);
  45 }
  46
  47 const struct brw_tracked_state gen7_tes_push_constants = {
  48    .dirty = {
  49       .mesa  = _NEW_PROGRAM_CONSTANTS,
  50       .brw   = BRW_NEW_BATCH |
  51                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  52                BRW_NEW_TESS_PROGRAMS |
  53                BRW_NEW_TES_PROG_DATA,
  54    },
  55    .emit = gen7_upload_tes_push_constants,
  56 };
  57
  58 static void
  59 gen7_upload_ds_state(struct brw_context *brw)
  60 {
  61    const struct brw_stage_state *stage_state = &brw->tes.base;
  62    /* BRW_NEW_TESS_PROGRAMS */
  63    bool active = brw->tess_eval_program;
  64
  65    /* BRW_NEW_TES_PROG_DATA */
  66    const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
  67    const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
  68    const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
  69
  70    const unsigned thread_count = (brw->max_ds_threads - 1) <<
  71       (brw->is_haswell ? HSW_DS_MAX_THREADS_SHIFT : GEN7_DS_MAX_THREADS_SHIFT);
  72
  73    if (active) {
  74       BEGIN_BATCH(6);
  75       OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
  76       OUT_BATCH(stage_state->prog_offset);
  77       OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
  78                           GEN7_DS_SAMPLER_COUNT) |
  79                 SET_FIELD(prog_data->binding_table.size_bytes / 4,
  80                           GEN7_DS_BINDING_TABLE_ENTRY_COUNT));
  81       if (prog_data->total_scratch) {
  82          OUT_RELOC(stage_state->scratch_bo,
  83                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  84                    ffs(prog_data->total_scratch) - 11);
  85       } else {
  86          OUT_BATCH(0);
  87       }
  88       OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
  89                           GEN7_DS_DISPATCH_START_GRF) |
  90                 SET_FIELD(vue_prog_data->urb_read_length,
  91                           GEN7_DS_URB_READ_LENGTH));
  92
  93       OUT_BATCH(GEN7_DS_ENABLE |
  94                 GEN7_DS_STATISTICS_ENABLE |
  95                 thread_count |
  96                 (tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
  97                  GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0));
  98       ADVANCE_BATCH();
  99    } else {
 100       BEGIN_BATCH(6);
 101       OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 102       OUT_BATCH(0);
 103       OUT_BATCH(0);
 104       OUT_BATCH(0);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       ADVANCE_BATCH();
 108    }
 109    brw->tes.enabled = active;
 110 }
 111
 112 const struct brw_tracked_state gen7_ds_state = {
 113    .dirty = {
 114       .mesa  = _NEW_TRANSFORM,
 115       .brw   = BRW_NEW_BATCH |
 116                BRW_NEW_CONTEXT |
 117                BRW_NEW_TESS_PROGRAMS |
 118                BRW_NEW_TES_PROG_DATA,
 119    },
 120    .emit = gen7_upload_ds_state,
 121 };