src/mesa/drivers/dri/i965/gen7_gs_state.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29
  30 static void
  31 gen7_upload_gs_push_constants(struct brw_context *brw)
  32 {
  33    const struct brw_stage_state *stage_state = &brw->gs.base;
  34    /* BRW_NEW_GEOMETRY_PROGRAM */
  35    const struct brw_geometry_program *gp =
  36       (struct brw_geometry_program *) brw->geometry_program;
  37
  38    if (gp) {
  39       /* CACHE_NEW_GS_PROG */
  40       const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
  41       struct brw_stage_state *stage_state = &brw->gs.base;
  42
  43       gen6_upload_vec4_push_constants(brw, &gp->program.Base, prog_data,
  44                                       stage_state, AUB_TRACE_VS_CONSTANTS);
  45    }
  46
  47    gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
  48 }
  49
  50 const struct brw_tracked_state gen7_gs_push_constants = {
  51    .dirty = {
  52       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
  53       .brw   = (BRW_NEW_BATCH |
  54                 BRW_NEW_GEOMETRY_PROGRAM |
  55                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
  56       .cache = CACHE_NEW_GS_PROG,
  57    },
  58    .emit = gen7_upload_gs_push_constants,
  59 };
  60
  61
  62 static void
  63 upload_gs_state(struct brw_context *brw)
  64 {
  65    const struct brw_stage_state *stage_state = &brw->gs.base;
  66    const int max_threads_shift = brw->is_haswell ?
  67       HSW_GS_MAX_THREADS_SHIFT : GEN6_GS_MAX_THREADS_SHIFT;
  68    /* BRW_NEW_GEOMETRY_PROGRAM */
  69    bool active = brw->geometry_program;
  70    /* CACHE_NEW_GS_PROG */
  71    const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
  72
  73    /**
  74     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
  75     * Geometry > Geometry Shader > State:
  76     *
  77     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
  78     *     whole fixed function pipeline when the GS enable changes value in
  79     *     the 3DSTATE_GS."
  80     *
  81     * The hardware architects have clarified that in this context "flush the
  82     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
  83     * Stall" bit set.
  84     */
  85    if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled != active)
  86       gen7_emit_cs_stall_flush(brw);
  87
  88    if (active) {
  89       BEGIN_BATCH(7);
  90       OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
  91       OUT_BATCH(stage_state->prog_offset);
  92       OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) <<
  93                  GEN6_GS_SAMPLER_COUNT_SHIFT) |
  94                 ((brw->gs.prog_data->base.base.binding_table.size_bytes / 4) <<
  95                  GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  96
  97       if (brw->gs.prog_data->base.total_scratch) {
  98          OUT_RELOC(stage_state->scratch_bo,
  99                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 100                    ffs(brw->gs.prog_data->base.total_scratch) - 11);
 101       } else {
 102          OUT_BATCH(0);
 103       }
 104
 105       uint32_t dw4 =
 106          ((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
 107           GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
 108          (brw->gs.prog_data->output_topology <<
 109           GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
 110          (prog_data->urb_read_length <<
 111           GEN6_GS_URB_READ_LENGTH_SHIFT) |
 112          (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
 113          (prog_data->dispatch_grf_start_reg <<
 114           GEN6_GS_DISPATCH_START_GRF_SHIFT);
 115
 116       /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
 117        * Ivy Bridge and Haswell.
 118        *
 119        * On Ivy Bridge, setting this bit causes the vertices of a triangle
 120        * strip to be delivered to the geometry shader in an order that does
 121        * not strictly follow the OpenGL spec, but preserves triangle
 122        * orientation.  For example, if the vertices are (1, 2, 3, 4, 5), then
 123        * the geometry shader sees triangles:
 124        *
 125        * (1, 2, 3), (2, 4, 3), (3, 4, 5)
 126        *
 127        * (Clearing the bit is even worse, because it fails to preserve
 128        * orientation).
 129        *
 130        * Triangle strips with adjacency always ordered in a way that preserves
 131        * triangle orientation but does not strictly follow the OpenGL spec,
 132        * regardless of the setting of this bit.
 133        *
 134        * On Haswell, both triangle strips and triangle strips with adjacency
 135        * are always ordered in a way that preserves triangle orientation.
 136        * Setting this bit causes the ordering to strictly follow the OpenGL
 137        * spec.
 138        *
 139        * So in either case we want to set the bit.  Unfortunately on Ivy
 140        * Bridge this will get the order close to correct but not perfect.
 141        */
 142       uint32_t dw5 =
 143          ((brw->max_gs_threads - 1) << max_threads_shift) |
 144          (brw->gs.prog_data->control_data_header_size_hwords <<
 145           GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
 146          ((brw->gs.prog_data->invocations - 1) <<
 147           GEN7_GS_INSTANCE_CONTROL_SHIFT) |
 148          (brw->gs.prog_data->dual_instanced_dispatch ?
 149           GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE :
 150           GEN7_GS_DISPATCH_MODE_DUAL_OBJECT) |
 151          GEN6_GS_STATISTICS_ENABLE |
 152          (brw->gs.prog_data->include_primitive_id ?
 153           GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
 154          GEN7_GS_REORDER_TRAILING |
 155          GEN7_GS_ENABLE;
 156       uint32_t dw6 = 0;
 157
 158       if (brw->is_haswell) {
 159          dw6 |= brw->gs.prog_data->control_data_format <<
 160             HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
 161       } else {
 162          dw5 |= brw->gs.prog_data->control_data_format <<
 163             IVB_GS_CONTROL_DATA_FORMAT_SHIFT;
 164       }
 165
 166       OUT_BATCH(dw4);
 167       OUT_BATCH(dw5);
 168       OUT_BATCH(dw6);
 169       ADVANCE_BATCH();
 170    } else {
 171       BEGIN_BATCH(7);
 172       OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 173       OUT_BATCH(0); /* prog_bo */
 174       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
 175                 (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 176       OUT_BATCH(0); /* scratch space base offset */
 177       OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
 178                 (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
 179                 GEN7_GS_INCLUDE_VERTEX_HANDLES |
 180                 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
 181       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
 182                 GEN6_GS_STATISTICS_ENABLE);
 183       OUT_BATCH(0);
 184       ADVANCE_BATCH();
 185    }
 186    brw->gs.enabled = active;
 187 }
 188
 189 const struct brw_tracked_state gen7_gs_state = {
 190    .dirty = {
 191       .mesa  = _NEW_TRANSFORM,
 192       .brw   = (BRW_NEW_CONTEXT |
 193                 BRW_NEW_GEOMETRY_PROGRAM |
 194                 BRW_NEW_BATCH),
 195       .cache = CACHE_NEW_GS_PROG
 196    },
 197    .emit = upload_gs_state,
 198 };