src/mesa/drivers/dri/i965/gen7_gs_state.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29
  30 static void
  31 gen7_upload_gs_push_constants(struct brw_context *brw)
  32 {
  33    /* BRW_NEW_GEOMETRY_PROGRAM */
  34    const struct brw_geometry_program *vp =
  35       (struct brw_geometry_program *) brw->geometry_program;
  36    if (!vp)
  37       return;
  38
  39    /* CACHE_NEW_GS_PROG */
  40    const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
  41    struct brw_stage_state *stage_state = &brw->gs.base;
  42
  43    gen6_upload_vec4_push_constants(brw, &vp->program.Base, prog_data,
  44                                    stage_state, AUB_TRACE_VS_CONSTANTS);
  45 }
  46
  47 const struct brw_tracked_state gen7_gs_push_constants = {
  48    .dirty = {
  49       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
  50       .brw   = (BRW_NEW_BATCH |
  51                 BRW_NEW_GEOMETRY_PROGRAM),
  52       .cache = CACHE_NEW_GS_PROG,
  53    },
  54    .emit = gen7_upload_gs_push_constants,
  55 };
  56
  57
  58 static void
  59 upload_gs_state(struct brw_context *brw)
  60 {
  61    const struct brw_stage_state *stage_state = &brw->gs.base;
  62    const int max_threads_shift = brw->is_haswell ?
  63       HSW_GS_MAX_THREADS_SHIFT : GEN6_GS_MAX_THREADS_SHIFT;
  64    /* BRW_NEW_GEOMETRY_PROGRAM */
  65    bool active = brw->geometry_program;
  66    /* CACHE_NEW_GS_PROG */
  67    const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
  68
  69    /* BRW_NEW_GS_BINDING_TABLE */
  70    BEGIN_BATCH(2);
  71    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
  72    OUT_BATCH(stage_state->bind_bo_offset);
  73    ADVANCE_BATCH();
  74
  75    /* CACHE_NEW_SAMPLER */
  76    BEGIN_BATCH(2);
  77    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_GS << 16 | (2 - 2));
  78    OUT_BATCH(stage_state->sampler_offset);
  79    ADVANCE_BATCH();
  80
  81    gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_GS);
  82
  83    /**
  84     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
  85     * Geometry > Geometry Shader > State:
  86     *
  87     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
  88     *     whole fixed function pipeline when the GS enable changes value in
  89     *     the 3DSTATE_GS."
  90     *
  91     * The hardware architects have clarified that in this context "flush the
  92     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
  93     * Stall" bit set.
  94     */
  95    if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled != active)
  96       gen7_emit_cs_stall_flush(brw);
  97
  98    if (active) {
  99       BEGIN_BATCH(7);
 100       OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 101       OUT_BATCH(stage_state->prog_offset);
 102       OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) <<
 103                  GEN6_GS_SAMPLER_COUNT_SHIFT) |
 104                 ((brw->gs.prog_data->base.base.binding_table.size_bytes / 4) <<
 105                  GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 106
 107       if (brw->gs.prog_data->base.total_scratch) {
 108          OUT_RELOC(stage_state->scratch_bo,
 109                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 110                    ffs(brw->gs.prog_data->base.total_scratch) - 11);
 111       } else {
 112          OUT_BATCH(0);
 113       }
 114
 115       uint32_t dw4 =
 116          ((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
 117           GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
 118          (brw->gs.prog_data->output_topology <<
 119           GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
 120          (prog_data->urb_read_length <<
 121           GEN6_GS_URB_READ_LENGTH_SHIFT) |
 122          (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
 123          (prog_data->dispatch_grf_start_reg <<
 124           GEN6_GS_DISPATCH_START_GRF_SHIFT);
 125
 126       /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
 127        * Ivy Bridge and Haswell.
 128        *
 129        * On Ivy Bridge, setting this bit causes the vertices of a triangle
 130        * strip to be delivered to the geometry shader in an order that does
 131        * not strictly follow the OpenGL spec, but preserves triangle
 132        * orientation.  For example, if the vertices are (1, 2, 3, 4, 5), then
 133        * the geometry shader sees triangles:
 134        *
 135        * (1, 2, 3), (2, 4, 3), (3, 4, 5)
 136        *
 137        * (Clearing the bit is even worse, because it fails to preserve
 138        * orientation).
 139        *
 140        * Triangle strips with adjacency always ordered in a way that preserves
 141        * triangle orientation but does not strictly follow the OpenGL spec,
 142        * regardless of the setting of this bit.
 143        *
 144        * On Haswell, both triangle strips and triangle strips with adjacency
 145        * are always ordered in a way that preserves triangle orientation.
 146        * Setting this bit causes the ordering to strictly follow the OpenGL
 147        * spec.
 148        *
 149        * So in either case we want to set the bit.  Unfortunately on Ivy
 150        * Bridge this will get the order close to correct but not perfect.
 151        */
 152       uint32_t dw5 =
 153          ((brw->max_gs_threads - 1) << max_threads_shift) |
 154          (brw->gs.prog_data->control_data_header_size_hwords <<
 155           GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
 156          ((brw->gs.prog_data->invocations - 1) <<
 157           GEN7_GS_INSTANCE_CONTROL_SHIFT) |
 158          (brw->gs.prog_data->dual_instanced_dispatch ?
 159           GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE :
 160           GEN7_GS_DISPATCH_MODE_DUAL_OBJECT) |
 161          GEN6_GS_STATISTICS_ENABLE |
 162          (brw->gs.prog_data->include_primitive_id ?
 163           GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
 164          GEN7_GS_REORDER_TRAILING |
 165          GEN7_GS_ENABLE;
 166       uint32_t dw6 = 0;
 167
 168       if (brw->is_haswell) {
 169          dw6 |= brw->gs.prog_data->control_data_format <<
 170             HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
 171       } else {
 172          dw5 |= brw->gs.prog_data->control_data_format <<
 173             IVB_GS_CONTROL_DATA_FORMAT_SHIFT;
 174       }
 175
 176       OUT_BATCH(dw4);
 177       OUT_BATCH(dw5);
 178       OUT_BATCH(dw6);
 179       ADVANCE_BATCH();
 180    } else {
 181       BEGIN_BATCH(7);
 182       OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 183       OUT_BATCH(0); /* prog_bo */
 184       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
 185                 (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 186       OUT_BATCH(0); /* scratch space base offset */
 187       OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
 188                 (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
 189                 GEN7_GS_INCLUDE_VERTEX_HANDLES |
 190                 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
 191       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
 192                 GEN6_GS_STATISTICS_ENABLE);
 193       OUT_BATCH(0);
 194       ADVANCE_BATCH();
 195    }
 196    brw->gs.enabled = active;
 197 }
 198
 199 const struct brw_tracked_state gen7_gs_state = {
 200    .dirty = {
 201       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 202       .brw   = (BRW_NEW_CONTEXT |
 203                 BRW_NEW_GEOMETRY_PROGRAM |
 204                 BRW_NEW_GS_BINDING_TABLE |
 205                 BRW_NEW_BATCH |
 206                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 207       .cache = CACHE_NEW_GS_PROG | CACHE_NEW_SAMPLER
 208    },
 209    .emit = upload_gs_state,
 210 };