src/mesa/drivers/dri/i965/gen7_hs_state.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29 static void
  30 gen7_upload_tcs_push_constants(struct brw_context *brw)
  31 {
  32    struct brw_stage_state *stage_state = &brw->tcs.base;
  33    /* BRW_NEW_TESS_PROGRAMS */
  34    const struct brw_tess_ctrl_program *tcp =
  35       (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
  36    bool active = brw->tess_eval_program;
  37
  38    if (active) {
  39       /* BRW_NEW_TCS_PROG_DATA */
  40       const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
  41       gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
  42                                       stage_state, AUB_TRACE_VS_CONSTANTS);
  43    }
  44
  45    gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS);
  46 }
  47
  48 const struct brw_tracked_state gen7_tcs_push_constants = {
  49    .dirty = {
  50       .mesa  = _NEW_PROGRAM_CONSTANTS,
  51       .brw   = BRW_NEW_BATCH |
  52                BRW_NEW_DEFAULT_TESS_LEVELS |
  53                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  54                BRW_NEW_TESS_PROGRAMS |
  55                BRW_NEW_TCS_PROG_DATA,
  56    },
  57    .emit = gen7_upload_tcs_push_constants,
  58 };
  59
  60 static void
  61 gen7_upload_hs_state(struct brw_context *brw)
  62 {
  63    const struct brw_stage_state *stage_state = &brw->tcs.base;
  64    /* BRW_NEW_TESS_PROGRAMS */
  65    bool active = brw->tess_eval_program;
  66    /* BRW_NEW_TCS_PROG_DATA */
  67    const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
  68
  69    if (active) {
  70       BEGIN_BATCH(7);
  71       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  72       OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
  73                           GEN7_HS_SAMPLER_COUNT) |
  74                 SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
  75                           GEN7_HS_BINDING_TABLE_ENTRY_COUNT) |
  76                 (brw->max_hs_threads - 1));
  77       OUT_BATCH(GEN7_HS_ENABLE |
  78                 GEN7_HS_STATISTICS_ENABLE |
  79                 SET_FIELD(brw->tcs.prog_data->instances - 1,
  80                           GEN7_HS_INSTANCE_COUNT));
  81       OUT_BATCH(stage_state->prog_offset);
  82       if (prog_data->base.total_scratch) {
  83          OUT_RELOC(stage_state->scratch_bo,
  84                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  85                    ffs(prog_data->base.total_scratch) - 11);
  86       } else {
  87          OUT_BATCH(0);
  88       }
  89       OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
  90                 SET_FIELD(prog_data->base.dispatch_grf_start_reg,
  91                           GEN7_HS_DISPATCH_START_GRF));
  92       /* Ignore URB semaphores */
  93       OUT_BATCH(0);
  94       ADVANCE_BATCH();
  95    } else {
  96       BEGIN_BATCH(7);
  97       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  98       OUT_BATCH(0);
  99       OUT_BATCH(0);
 100       OUT_BATCH(0);
 101       OUT_BATCH(0);
 102       OUT_BATCH(0);
 103       OUT_BATCH(0);
 104       ADVANCE_BATCH();
 105    }
 106    brw->tcs.enabled = active;
 107 }
 108
 109 const struct brw_tracked_state gen7_hs_state = {
 110    .dirty = {
 111       .mesa  = 0,
 112       .brw   = BRW_NEW_BATCH |
 113                BRW_NEW_TCS_PROG_DATA |
 114                BRW_NEW_TESS_PROGRAMS,
 115    },
 116    .emit = gen7_upload_hs_state,
 117 };