src/mesa/drivers/dri/i965/gen7_hs_state.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28 #include "main/shaderapi.h"
  29
  30 static void
  31 gen7_upload_tcs_push_constants(struct brw_context *brw)
  32 {
  33    struct brw_stage_state *stage_state = &brw->tcs.base;
  34    /* BRW_NEW_TESS_PROGRAMS */
  35    const struct brw_tess_ctrl_program *tcp =
  36       (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
  37    bool active = brw->tess_eval_program;
  38
  39    if (active) {
  40       /* BRW_NEW_TCS_PROG_DATA */
  41       const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
  42
  43       _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
  44       gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
  45                                       stage_state, AUB_TRACE_VS_CONSTANTS);
  46    }
  47
  48    gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS);
  49 }
  50
  51 const struct brw_tracked_state gen7_tcs_push_constants = {
  52    .dirty = {
  53       .mesa  = _NEW_PROGRAM_CONSTANTS,
  54       .brw   = BRW_NEW_BATCH |
  55                BRW_NEW_BLORP |
  56                BRW_NEW_DEFAULT_TESS_LEVELS |
  57                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  58                BRW_NEW_TESS_PROGRAMS |
  59                BRW_NEW_TCS_PROG_DATA,
  60    },
  61    .emit = gen7_upload_tcs_push_constants,
  62 };
  63
  64 static void
  65 gen7_upload_hs_state(struct brw_context *brw)
  66 {
  67    const struct brw_stage_state *stage_state = &brw->tcs.base;
  68    /* BRW_NEW_TESS_PROGRAMS */
  69    bool active = brw->tess_eval_program;
  70    /* BRW_NEW_TCS_PROG_DATA */
  71    const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
  72
  73    if (active) {
  74       BEGIN_BATCH(7);
  75       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  76       OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
  77                           GEN7_HS_SAMPLER_COUNT) |
  78                 SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
  79                           GEN7_HS_BINDING_TABLE_ENTRY_COUNT) |
  80                 (brw->max_hs_threads - 1));
  81       OUT_BATCH(GEN7_HS_ENABLE |
  82                 GEN7_HS_STATISTICS_ENABLE |
  83                 SET_FIELD(brw->tcs.prog_data->instances - 1,
  84                           GEN7_HS_INSTANCE_COUNT));
  85       OUT_BATCH(stage_state->prog_offset);
  86       if (prog_data->base.total_scratch) {
  87          OUT_RELOC(stage_state->scratch_bo,
  88                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  89                    ffs(stage_state->per_thread_scratch) - 11);
  90       } else {
  91          OUT_BATCH(0);
  92       }
  93       OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
  94                 SET_FIELD(prog_data->base.dispatch_grf_start_reg,
  95                           GEN7_HS_DISPATCH_START_GRF));
  96       /* Ignore URB semaphores */
  97       OUT_BATCH(0);
  98       ADVANCE_BATCH();
  99    } else {
 100       BEGIN_BATCH(7);
 101       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 102       OUT_BATCH(0);
 103       OUT_BATCH(0);
 104       OUT_BATCH(0);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       ADVANCE_BATCH();
 109    }
 110    brw->tcs.enabled = active;
 111 }
 112
 113 const struct brw_tracked_state gen7_hs_state = {
 114    .dirty = {
 115       .mesa  = 0,
 116       .brw   = BRW_NEW_BATCH |
 117                BRW_NEW_BLORP |
 118                BRW_NEW_TCS_PROG_DATA |
 119                BRW_NEW_TESS_PROGRAMS,
 120    },
 121    .emit = gen7_upload_hs_state,
 122 };