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24 #include "common/gen_l3_config.h"
26 #include "brw_context.h"
27 #include "brw_defines.h"
28 #include "brw_state.h"
29 #include "intel_batchbuffer.h"
32 * Calculate the desired L3 partitioning based on the current state of the
33 * pipeline. For now this simply returns the conservative defaults calculated
34 * by get_default_l3_weights(), but we could probably do better by gathering
35 * more statistics from the pipeline state (e.g. guess of expected URB usage
36 * and bound surfaces), or by using feed-back from performance counters.
38 static struct gen_l3_weights
39 get_pipeline_state_l3_weights(const struct brw_context
*brw
)
41 const struct brw_stage_state
*stage_states
[] = {
42 [MESA_SHADER_VERTEX
] = &brw
->vs
.base
,
43 [MESA_SHADER_TESS_CTRL
] = &brw
->tcs
.base
,
44 [MESA_SHADER_TESS_EVAL
] = &brw
->tes
.base
,
45 [MESA_SHADER_GEOMETRY
] = &brw
->gs
.base
,
46 [MESA_SHADER_FRAGMENT
] = &brw
->wm
.base
,
47 [MESA_SHADER_COMPUTE
] = &brw
->cs
.base
49 bool needs_dc
= false, needs_slm
= false;
51 for (unsigned i
= 0; i
< ARRAY_SIZE(stage_states
); i
++) {
52 const struct gl_program
*prog
=
53 brw
->ctx
._Shader
->CurrentProgram
[stage_states
[i
]->stage
];
54 const struct brw_stage_prog_data
*prog_data
= stage_states
[i
]->prog_data
;
56 needs_dc
|= (prog
&& (prog
->sh
.data
->NumAtomicBuffers
||
57 prog
->sh
.data
->NumShaderStorageBlocks
||
58 prog
->info
.num_images
)) ||
59 (prog_data
&& prog_data
->total_scratch
);
60 needs_slm
|= prog_data
&& prog_data
->total_shared
;
63 return gen_get_default_l3_weights(&brw
->screen
->devinfo
,
68 * Program the hardware to use the specified L3 configuration.
71 setup_l3_config(struct brw_context
*brw
, const struct gen_l3_config
*cfg
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
74 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
75 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
77 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
79 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
81 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
83 /* According to the hardware docs, the L3 partitioning can only be changed
84 * while the pipeline is completely drained and the caches are flushed,
85 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
87 brw_emit_pipe_control_flush(brw
,
88 PIPE_CONTROL_DATA_CACHE_FLUSH
|
89 PIPE_CONTROL_NO_WRITE
|
90 PIPE_CONTROL_CS_STALL
);
92 /* ...followed by a second pipelined PIPE_CONTROL that initiates
93 * invalidation of the relevant caches. Note that because RO invalidation
94 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
95 * command is processed by the CS) we cannot combine it with the previous
96 * stalling flush as the hardware documentation suggests, because that
97 * would cause the CS to stall on previous rendering *after* RO
98 * invalidation and wouldn't prevent the RO caches from being polluted by
99 * concurrent rendering before the stall completes. This intentionally
100 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
101 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
102 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
103 * already guarantee that there is no concurrent GPGPU kernel execution
104 * (see SKL HSD 2132585).
106 brw_emit_pipe_control_flush(brw
,
107 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
108 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
109 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
110 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
111 PIPE_CONTROL_NO_WRITE
);
113 /* Now send a third stalling flush to make sure that invalidation is
114 * complete when the L3 configuration registers are modified.
116 brw_emit_pipe_control_flush(brw
,
117 PIPE_CONTROL_DATA_CACHE_FLUSH
|
118 PIPE_CONTROL_NO_WRITE
|
119 PIPE_CONTROL_CS_STALL
);
121 if (devinfo
->gen
>= 8) {
122 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
125 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
127 /* Set up the L3 partitioning. */
128 OUT_BATCH(GEN8_L3CNTLREG
);
129 OUT_BATCH((has_slm
? GEN8_L3CNTLREG_SLM_ENABLE
: 0) |
130 SET_FIELD(cfg
->n
[GEN_L3P_URB
], GEN8_L3CNTLREG_URB_ALLOC
) |
131 SET_FIELD(cfg
->n
[GEN_L3P_RO
], GEN8_L3CNTLREG_RO_ALLOC
) |
132 SET_FIELD(cfg
->n
[GEN_L3P_DC
], GEN8_L3CNTLREG_DC_ALLOC
) |
133 SET_FIELD(cfg
->n
[GEN_L3P_ALL
], GEN8_L3CNTLREG_ALL_ALLOC
));
138 assert(!cfg
->n
[GEN_L3P_ALL
]);
140 /* When enabled SLM only uses a portion of the L3 on half of the banks,
141 * the matching space on the remaining banks has to be allocated to a
142 * client (URB for all validated configurations) set to the
143 * lower-bandwidth 2-bank address hashing mode.
145 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
146 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
148 /* Minimum number of ways that can be allocated to the URB. */
149 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
150 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
153 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (7 - 2));
155 /* Demote any clients with no ways assigned to LLC. */
156 OUT_BATCH(GEN7_L3SQCREG1
);
157 OUT_BATCH((devinfo
->is_haswell
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
158 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
159 IVB_L3SQCREG1_SQGHPCI_DEFAULT
) |
160 (has_dc
? 0 : GEN7_L3SQCREG1_CONV_DC_UC
) |
161 (has_is
? 0 : GEN7_L3SQCREG1_CONV_IS_UC
) |
162 (has_c
? 0 : GEN7_L3SQCREG1_CONV_C_UC
) |
163 (has_t
? 0 : GEN7_L3SQCREG1_CONV_T_UC
));
165 /* Set up the L3 partitioning. */
166 OUT_BATCH(GEN7_L3CNTLREG2
);
167 OUT_BATCH((has_slm
? GEN7_L3CNTLREG2_SLM_ENABLE
: 0) |
168 SET_FIELD(cfg
->n
[GEN_L3P_URB
] - n0_urb
, GEN7_L3CNTLREG2_URB_ALLOC
) |
169 (urb_low_bw
? GEN7_L3CNTLREG2_URB_LOW_BW
: 0) |
170 SET_FIELD(cfg
->n
[GEN_L3P_ALL
], GEN7_L3CNTLREG2_ALL_ALLOC
) |
171 SET_FIELD(cfg
->n
[GEN_L3P_RO
], GEN7_L3CNTLREG2_RO_ALLOC
) |
172 SET_FIELD(cfg
->n
[GEN_L3P_DC
], GEN7_L3CNTLREG2_DC_ALLOC
));
173 OUT_BATCH(GEN7_L3CNTLREG3
);
174 OUT_BATCH(SET_FIELD(cfg
->n
[GEN_L3P_IS
], GEN7_L3CNTLREG3_IS_ALLOC
) |
175 SET_FIELD(cfg
->n
[GEN_L3P_C
], GEN7_L3CNTLREG3_C_ALLOC
) |
176 SET_FIELD(cfg
->n
[GEN_L3P_T
], GEN7_L3CNTLREG3_T_ALLOC
));
180 if (can_do_hsw_l3_atomics(brw
->screen
)) {
181 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
182 * them disabled to avoid crashing the system hard.
185 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
186 OUT_BATCH(HSW_SCRATCH1
);
187 OUT_BATCH(has_dc
? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE
);
188 OUT_BATCH(HSW_ROW_CHICKEN3
);
189 OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE
) |
190 (has_dc
? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE
));
197 * Update the URB size in the context state for the specified L3
201 update_urb_size(struct brw_context
*brw
, const struct gen_l3_config
*cfg
)
203 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
204 const unsigned sz
= gen_get_l3_config_urb_size(devinfo
, cfg
);
206 if (brw
->urb
.size
!= sz
) {
208 brw
->ctx
.NewDriverState
|= BRW_NEW_URB_SIZE
;
210 /* If we change the total URB size, reset the individual stage sizes to
211 * zero so that, even if there is no URB size change, gen7_upload_urb
212 * still re-emits 3DSTATE_URB_*.
222 emit_l3_state(struct brw_context
*brw
)
224 const struct gen_l3_weights w
= get_pipeline_state_l3_weights(brw
);
225 const float dw
= gen_diff_l3_weights(w
, gen_get_l3_config_weights(brw
->l3
.config
));
226 /* The distance between any two compatible weight vectors cannot exceed two
227 * due to the triangle inequality.
229 const float large_dw_threshold
= 2.0;
230 /* Somewhat arbitrary, simply makes sure that there will be no repeated
231 * transitions to the same L3 configuration, could probably do better here.
233 const float small_dw_threshold
= 0.5;
234 /* If we're emitting a new batch the caches should already be clean and the
235 * transition should be relatively cheap, so it shouldn't hurt much to use
236 * the smaller threshold. Otherwise use the larger threshold so that we
237 * only reprogram the L3 mid-batch if the most recently programmed
238 * configuration is incompatible with the current pipeline state.
240 const float dw_threshold
= (brw
->ctx
.NewDriverState
& BRW_NEW_BATCH
?
241 small_dw_threshold
: large_dw_threshold
);
243 if (dw
> dw_threshold
&& can_do_pipelined_register_writes(brw
->screen
)) {
244 const struct gen_l3_config
*const cfg
=
245 gen_get_l3_config(&brw
->screen
->devinfo
, w
);
247 setup_l3_config(brw
, cfg
);
248 update_urb_size(brw
, cfg
);
249 brw
->l3
.config
= cfg
;
251 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
252 fprintf(stderr
, "L3 config transition (%f > %f): ", dw
, dw_threshold
);
253 gen_dump_l3_config(cfg
, stderr
);
258 const struct brw_tracked_state gen7_l3_state
= {
261 .brw
= BRW_NEW_BATCH
|
263 BRW_NEW_CS_PROG_DATA
|
264 BRW_NEW_FS_PROG_DATA
|
265 BRW_NEW_GS_PROG_DATA
|
266 BRW_NEW_VS_PROG_DATA
,
268 .emit
= emit_l3_state
272 * Hack to restore the default L3 configuration.
274 * This will be called at the end of every batch in order to reset the L3
275 * configuration to the default values for the time being until the kernel is
276 * fixed. Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
277 * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting
278 * batch buffers for the default context used by the DDX, which meant that any
279 * context state changed by the GL would leak into the DDX, the assumption
280 * being that the DDX would initialize any state it cares about manually. The
281 * DDX is however not careful enough to program an L3 configuration
282 * explicitly, and it makes assumptions about it (URB size) which won't hold
283 * and cause it to misrender if we let our L3 set-up to leak into the DDX.
285 * Since v4.1 of the Linux kernel the default context is saved and restored
286 * normally, so it's far less likely for our L3 programming to interfere with
287 * other contexts -- In fact restoring the default L3 configuration at the end
288 * of the batch will be redundant most of the time. A kind of state leak is
289 * still possible though if the context making assumptions about L3 state is
290 * created immediately after our context was active (e.g. without the DDX
291 * default context being scheduled in between) because at present the DRM
292 * doesn't fully initialize the contents of newly created contexts and instead
293 * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the
294 * last active context.
296 * It's possible to realize such a scenario if, say, an X server (or a GL
297 * application using an outdated non-L3-aware Mesa version) is started while
298 * another GL application is running and happens to have modified the L3
299 * configuration, or if no X server is running at all and a GL application
300 * using a non-L3-aware Mesa version is started after another GL application
301 * ran and modified the L3 configuration -- The latter situation can actually
302 * be reproduced easily on IVB in our CI system.
305 gen7_restore_default_l3_config(struct brw_context
*brw
)
307 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
308 const struct gen_l3_config
*const cfg
= gen_get_default_l3_config(devinfo
);
310 if (cfg
!= brw
->l3
.config
&&
311 can_do_pipelined_register_writes(brw
->screen
)) {
312 setup_l3_config(brw
, cfg
);
313 update_urb_size(brw
, cfg
);
314 brw
->l3
.config
= cfg
;