src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_defines.h"
  26 #include "brw_state.h"
  27 #include "intel_batchbuffer.h"
  28
  29 /**
  30  * Chunk of L3 cache reserved for some specific purpose.
  31  */
  32 enum brw_l3_partition {
  33    /** Shared local memory. */
  34    L3P_SLM = 0,
  35    /** Unified return buffer. */
  36    L3P_URB,
  37    /** Union of DC and RO. */
  38    L3P_ALL,
  39    /** Data cluster RW partition. */
  40    L3P_DC,
  41    /** Union of IS, C and T. */
  42    L3P_RO,
  43    /** Instruction and state cache. */
  44    L3P_IS,
  45    /** Constant cache. */
  46    L3P_C,
  47    /** Texture cache. */
  48    L3P_T,
  49    /** Number of supported L3 partitions. */
  50    NUM_L3P
  51 };
  52
  53 /**
  54  * L3 configuration represented as the number of ways allocated for each
  55  * partition.  \sa get_l3_way_size().
  56  */
  57 struct brw_l3_config {
  58    unsigned n[NUM_L3P];
  59 };
  60
  61 /**
  62  * IVB/HSW validated L3 configurations.
  63  */
  64 static const struct brw_l3_config ivb_l3_configs[] = {
  65    /* SLM URB ALL DC  RO  IS   C   T */
  66    {{  0, 32,  0,  0, 32,  0,  0,  0 }},
  67    {{  0, 32,  0, 16, 16,  0,  0,  0 }},
  68    {{  0, 32,  0,  4,  0,  8,  4, 16 }},
  69    {{  0, 28,  0,  8,  0,  8,  4, 16 }},
  70    {{  0, 28,  0, 16,  0,  8,  4,  8 }},
  71    {{  0, 28,  0,  8,  0, 16,  4,  8 }},
  72    {{  0, 28,  0,  0,  0, 16,  4, 16 }},
  73    {{  0, 32,  0,  0,  0, 16,  0, 16 }},
  74    {{  0, 28,  0,  4, 32,  0,  0,  0 }},
  75    {{ 16, 16,  0, 16, 16,  0,  0,  0 }},
  76    {{ 16, 16,  0,  8,  0,  8,  8,  8 }},
  77    {{ 16, 16,  0,  4,  0,  8,  4, 16 }},
  78    {{ 16, 16,  0,  4,  0, 16,  4,  8 }},
  79    {{ 16, 16,  0,  0, 32,  0,  0,  0 }},
  80    {{ 0 }}
  81 };
  82
  83 /**
  84  * VLV validated L3 configurations.
  85  */
  86 static const struct brw_l3_config vlv_l3_configs[] = {
  87    /* SLM URB ALL DC  RO  IS   C   T */
  88    {{  0, 64,  0,  0, 32,  0,  0,  0 }},
  89    {{  0, 80,  0,  0, 16,  0,  0,  0 }},
  90    {{  0, 80,  0,  8,  8,  0,  0,  0 }},
  91    {{  0, 64,  0, 16, 16,  0,  0,  0 }},
  92    {{  0, 60,  0,  4, 32,  0,  0,  0 }},
  93    {{ 32, 32,  0, 16, 16,  0,  0,  0 }},
  94    {{ 32, 40,  0,  8, 16,  0,  0,  0 }},
  95    {{ 32, 40,  0, 16,  8,  0,  0,  0 }},
  96    {{ 0 }}
  97 };
  98
  99 /**
 100  * BDW validated L3 configurations.
 101  */
 102 static const struct brw_l3_config bdw_l3_configs[] = {
 103    /* SLM URB ALL DC  RO  IS   C   T */
 104    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 105    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 106    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 107    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 108    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 109    {{ 24, 16, 48,  0,  0,  0,  0,  0 }},
 110    {{ 24, 16,  0, 16, 32,  0,  0,  0 }},
 111    {{ 24, 16,  0, 32, 16,  0,  0,  0 }},
 112    {{ 0 }}
 113 };
 114
 115 /**
 116  * CHV/SKL validated L3 configurations.
 117  */
 118 static const struct brw_l3_config chv_l3_configs[] = {
 119    /* SLM URB ALL DC  RO  IS   C   T */
 120    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 121    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 122    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 123    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 124    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 125    {{ 32, 16, 48,  0,  0,  0,  0,  0 }},
 126    {{ 32, 16,  0, 16, 32,  0,  0,  0 }},
 127    {{ 32, 16,  0, 32, 16,  0,  0,  0 }},
 128    {{ 0 }}
 129 };
 130
 131 /**
 132  * Return a zero-terminated array of validated L3 configurations for the
 133  * specified device.
 134  */
 135 static const struct brw_l3_config *
 136 get_l3_configs(const struct brw_device_info *devinfo)
 137 {
 138    switch (devinfo->gen) {
 139    case 7:
 140       return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
 141
 142    case 8:
 143       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 144
 145    case 9:
 146       return chv_l3_configs;
 147
 148    default:
 149       unreachable("Not implemented");
 150    }
 151 }
 152
 153 /**
 154  * Return the size of an L3 way in KB.
 155  */
 156 static unsigned
 157 get_l3_way_size(const struct brw_device_info *devinfo)
 158 {
 159    if (devinfo->is_baytrail)
 160       return 2;
 161
 162    else if (devinfo->is_cherryview || devinfo->gt == 1)
 163       return 4;
 164
 165    else
 166       return 8 * devinfo->num_slices;
 167 }
 168
 169 /**
 170  * Program the hardware to use the specified L3 configuration.
 171  */
 172 static void
 173 setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
 174 {
 175    const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
 176    const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 177    const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 178    const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 179    const bool has_slm = cfg->n[L3P_SLM];
 180
 181    /* According to the hardware docs, the L3 partitioning can only be changed
 182     * while the pipeline is completely drained and the caches are flushed,
 183     * which involves a first PIPE_CONTROL flush which stalls the pipeline and
 184     * initiates invalidation of the relevant caches...
 185     */
 186    brw_emit_pipe_control_flush(brw,
 187                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 188                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 189                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 190                                PIPE_CONTROL_DATA_CACHE_INVALIDATE |
 191                                PIPE_CONTROL_NO_WRITE |
 192                                PIPE_CONTROL_CS_STALL);
 193
 194    /* ...followed by a second stalling flush which guarantees that
 195     * invalidation is complete when the L3 configuration registers are
 196     * modified.
 197     */
 198    brw_emit_pipe_control_flush(brw,
 199                                PIPE_CONTROL_DATA_CACHE_INVALIDATE |
 200                                PIPE_CONTROL_NO_WRITE |
 201                                PIPE_CONTROL_CS_STALL);
 202
 203    if (brw->gen >= 8) {
 204       assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
 205
 206       BEGIN_BATCH(3);
 207       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 208
 209       /* Set up the L3 partitioning. */
 210       OUT_BATCH(GEN8_L3CNTLREG);
 211       OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
 212                 SET_FIELD(cfg->n[L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
 213                 SET_FIELD(cfg->n[L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
 214                 SET_FIELD(cfg->n[L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
 215                 SET_FIELD(cfg->n[L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 216
 217       ADVANCE_BATCH();
 218
 219    } else {
 220       assert(!cfg->n[L3P_ALL]);
 221
 222       /* When enabled SLM only uses a portion of the L3 on half of the banks,
 223        * the matching space on the remaining banks has to be allocated to a
 224        * client (URB for all validated configurations) set to the
 225        * lower-bandwidth 2-bank address hashing mode.
 226        */
 227       const bool urb_low_bw = has_slm && !brw->is_baytrail;
 228       assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
 229
 230       /* Minimum number of ways that can be allocated to the URB. */
 231       const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
 232       assert(cfg->n[L3P_URB] >= n0_urb);
 233
 234       BEGIN_BATCH(7);
 235       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
 236
 237       /* Demote any clients with no ways assigned to LLC. */
 238       OUT_BATCH(GEN7_L3SQCREG1);
 239       OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
 240                  brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
 241                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
 242                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
 243                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
 244                 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
 245                 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
 246
 247       /* Set up the L3 partitioning. */
 248       OUT_BATCH(GEN7_L3CNTLREG2);
 249       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
 250                 SET_FIELD(cfg->n[L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
 251                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
 252                 SET_FIELD(cfg->n[L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
 253                 SET_FIELD(cfg->n[L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
 254                 SET_FIELD(cfg->n[L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
 255       OUT_BATCH(GEN7_L3CNTLREG3);
 256       OUT_BATCH(SET_FIELD(cfg->n[L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
 257                 SET_FIELD(cfg->n[L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
 258                 SET_FIELD(cfg->n[L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 259
 260       ADVANCE_BATCH();
 261
 262       if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) {
 263          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
 264           * them disabled to avoid crashing the system hard.
 265           */
 266          BEGIN_BATCH(5);
 267          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
 268          OUT_BATCH(HSW_SCRATCH1);
 269          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
 270          OUT_BATCH(HSW_ROW_CHICKEN3);
 271          OUT_BATCH(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE << 16 |
 272                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
 273          ADVANCE_BATCH();
 274       }
 275    }
 276 }