src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "common/gen_l3_config.h"
  25
  26 #include "brw_context.h"
  27 #include "brw_defines.h"
  28 #include "brw_state.h"
  29 #include "intel_batchbuffer.h"
  30
  31 /**
  32  * Calculate the desired L3 partitioning based on the current state of the
  33  * pipeline.  For now this simply returns the conservative defaults calculated
  34  * by get_default_l3_weights(), but we could probably do better by gathering
  35  * more statistics from the pipeline state (e.g. guess of expected URB usage
  36  * and bound surfaces), or by using feed-back from performance counters.
  37  */
  38 static struct gen_l3_weights
  39 get_pipeline_state_l3_weights(const struct brw_context *brw)
  40 {
  41    const struct brw_stage_state *stage_states[] = {
  42       [MESA_SHADER_VERTEX] = &brw->vs.base,
  43       [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
  44       [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
  45       [MESA_SHADER_GEOMETRY] = &brw->gs.base,
  46       [MESA_SHADER_FRAGMENT] = &brw->wm.base,
  47       [MESA_SHADER_COMPUTE] = &brw->cs.base
  48    };
  49    bool needs_dc = false, needs_slm = false;
  50
  51    for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
  52       const struct gl_program *prog =
  53          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
  54       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
  55
  56       needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers ||
  57                             prog->sh.data->NumShaderStorageBlocks ||
  58                             prog->info.num_images)) ||
  59          (prog_data && prog_data->total_scratch);
  60       needs_slm |= prog_data && prog_data->total_shared;
  61    }
  62
  63    return gen_get_default_l3_weights(&brw->screen->devinfo,
  64                                      needs_dc, needs_slm);
  65 }
  66
  67 /**
  68  * Program the hardware to use the specified L3 configuration.
  69  */
  70 static void
  71 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
  72 {
  73    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  74    const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
  75    const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
  76                        cfg->n[GEN_L3P_ALL];
  77    const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
  78                       cfg->n[GEN_L3P_ALL];
  79    const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
  80                       cfg->n[GEN_L3P_ALL];
  81    const bool has_slm = cfg->n[GEN_L3P_SLM];
  82
  83    /* According to the hardware docs, the L3 partitioning can only be changed
  84     * while the pipeline is completely drained and the caches are flushed,
  85     * which involves a first PIPE_CONTROL flush which stalls the pipeline...
  86     */
  87    brw_emit_pipe_control_flush(brw,
  88                                PIPE_CONTROL_DATA_CACHE_FLUSH |
  89                                PIPE_CONTROL_CS_STALL);
  90
  91    /* ...followed by a second pipelined PIPE_CONTROL that initiates
  92     * invalidation of the relevant caches.  Note that because RO invalidation
  93     * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
  94     * command is processed by the CS) we cannot combine it with the previous
  95     * stalling flush as the hardware documentation suggests, because that
  96     * would cause the CS to stall on previous rendering *after* RO
  97     * invalidation and wouldn't prevent the RO caches from being polluted by
  98     * concurrent rendering before the stall completes.  This intentionally
  99     * doesn't implement the SKL+ hardware workaround suggesting to enable CS
 100     * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
 101     * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
 102     * already guarantee that there is no concurrent GPGPU kernel execution
 103     * (see SKL HSD 2132585).
 104     */
 105    brw_emit_pipe_control_flush(brw,
 106                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 107                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 108                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 109                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 110
 111    /* Now send a third stalling flush to make sure that invalidation is
 112     * complete when the L3 configuration registers are modified.
 113     */
 114    brw_emit_pipe_control_flush(brw,
 115                                PIPE_CONTROL_DATA_CACHE_FLUSH |
 116                                PIPE_CONTROL_CS_STALL);
 117
 118    if (devinfo->gen >= 8) {
 119       assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 120
 121       const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
 122          (devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
 123          SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
 124          SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
 125          SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
 126          SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 127
 128       /* Set up the L3 partitioning. */
 129       brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
 130    } else {
 131       assert(!cfg->n[GEN_L3P_ALL]);
 132
 133       /* When enabled SLM only uses a portion of the L3 on half of the banks,
 134        * the matching space on the remaining banks has to be allocated to a
 135        * client (URB for all validated configurations) set to the
 136        * lower-bandwidth 2-bank address hashing mode.
 137        */
 138       const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
 139       assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
 140
 141       /* Minimum number of ways that can be allocated to the URB. */
 142       const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
 143       assert(cfg->n[GEN_L3P_URB] >= n0_urb);
 144
 145       BEGIN_BATCH(7);
 146       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
 147
 148       /* Demote any clients with no ways assigned to LLC. */
 149       OUT_BATCH(GEN7_L3SQCREG1);
 150       OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
 151                  devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
 152                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
 153                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
 154                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
 155                 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
 156                 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
 157
 158       /* Set up the L3 partitioning. */
 159       OUT_BATCH(GEN7_L3CNTLREG2);
 160       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
 161                 SET_FIELD(cfg->n[GEN_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
 162                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
 163                 SET_FIELD(cfg->n[GEN_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
 164                 SET_FIELD(cfg->n[GEN_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
 165                 SET_FIELD(cfg->n[GEN_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
 166       OUT_BATCH(GEN7_L3CNTLREG3);
 167       OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
 168                 SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
 169                 SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 170
 171       ADVANCE_BATCH();
 172
 173       if (can_do_hsw_l3_atomics(brw->screen)) {
 174          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
 175           * them disabled to avoid crashing the system hard.
 176           */
 177          BEGIN_BATCH(5);
 178          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
 179          OUT_BATCH(HSW_SCRATCH1);
 180          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
 181          OUT_BATCH(HSW_ROW_CHICKEN3);
 182          OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
 183                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
 184          ADVANCE_BATCH();
 185       }
 186    }
 187 }
 188
 189 /**
 190  * Update the URB size in the context state for the specified L3
 191  * configuration.
 192  */
 193 static void
 194 update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
 195 {
 196    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 197    const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
 198
 199    if (brw->urb.size != sz) {
 200       brw->urb.size = sz;
 201       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 202
 203       /* If we change the total URB size, reset the individual stage sizes to
 204        * zero so that, even if there is no URB size change, gen7_upload_urb
 205        * still re-emits 3DSTATE_URB_*.
 206        */
 207       brw->urb.vsize = 0;
 208       brw->urb.gsize = 0;
 209       brw->urb.hsize = 0;
 210       brw->urb.dsize = 0;
 211    }
 212 }
 213
 214 static void
 215 emit_l3_state(struct brw_context *brw)
 216 {
 217    const struct gen_l3_weights w = get_pipeline_state_l3_weights(brw);
 218    const float dw = gen_diff_l3_weights(w, gen_get_l3_config_weights(brw->l3.config));
 219    /* The distance between any two compatible weight vectors cannot exceed two
 220     * due to the triangle inequality.
 221     */
 222    const float large_dw_threshold = 2.0;
 223    /* Somewhat arbitrary, simply makes sure that there will be no repeated
 224     * transitions to the same L3 configuration, could probably do better here.
 225     */
 226    const float small_dw_threshold = 0.5;
 227    /* If we're emitting a new batch the caches should already be clean and the
 228     * transition should be relatively cheap, so it shouldn't hurt much to use
 229     * the smaller threshold.  Otherwise use the larger threshold so that we
 230     * only reprogram the L3 mid-batch if the most recently programmed
 231     * configuration is incompatible with the current pipeline state.
 232     */
 233    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
 234                                small_dw_threshold : large_dw_threshold);
 235
 236    if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) {
 237       const struct gen_l3_config *const cfg =
 238          gen_get_l3_config(&brw->screen->devinfo, w);
 239
 240       setup_l3_config(brw, cfg);
 241       update_urb_size(brw, cfg);
 242       brw->l3.config = cfg;
 243
 244       if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
 245          fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
 246          gen_dump_l3_config(cfg, stderr);
 247       }
 248    }
 249 }
 250
 251 const struct brw_tracked_state gen7_l3_state = {
 252    .dirty = {
 253       .mesa = 0,
 254       .brw = BRW_NEW_BATCH |
 255              BRW_NEW_BLORP |
 256              BRW_NEW_CS_PROG_DATA |
 257              BRW_NEW_FS_PROG_DATA |
 258              BRW_NEW_GS_PROG_DATA |
 259              BRW_NEW_TCS_PROG_DATA |
 260              BRW_NEW_TES_PROG_DATA |
 261              BRW_NEW_VS_PROG_DATA,
 262    },
 263    .emit = emit_l3_state
 264 };
 265
 266 /**
 267  * Hack to restore the default L3 configuration.
 268  *
 269  * This will be called at the end of every batch in order to reset the L3
 270  * configuration to the default values for the time being until the kernel is
 271  * fixed.  Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
 272  * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting
 273  * batch buffers for the default context used by the DDX, which meant that any
 274  * context state changed by the GL would leak into the DDX, the assumption
 275  * being that the DDX would initialize any state it cares about manually.  The
 276  * DDX is however not careful enough to program an L3 configuration
 277  * explicitly, and it makes assumptions about it (URB size) which won't hold
 278  * and cause it to misrender if we let our L3 set-up to leak into the DDX.
 279  *
 280  * Since v4.1 of the Linux kernel the default context is saved and restored
 281  * normally, so it's far less likely for our L3 programming to interfere with
 282  * other contexts -- In fact restoring the default L3 configuration at the end
 283  * of the batch will be redundant most of the time.  A kind of state leak is
 284  * still possible though if the context making assumptions about L3 state is
 285  * created immediately after our context was active (e.g. without the DDX
 286  * default context being scheduled in between) because at present the DRM
 287  * doesn't fully initialize the contents of newly created contexts and instead
 288  * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the
 289  * last active context.
 290  *
 291  * It's possible to realize such a scenario if, say, an X server (or a GL
 292  * application using an outdated non-L3-aware Mesa version) is started while
 293  * another GL application is running and happens to have modified the L3
 294  * configuration, or if no X server is running at all and a GL application
 295  * using a non-L3-aware Mesa version is started after another GL application
 296  * ran and modified the L3 configuration -- The latter situation can actually
 297  * be reproduced easily on IVB in our CI system.
 298  */
 299 void
 300 gen7_restore_default_l3_config(struct brw_context *brw)
 301 {
 302    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 303    const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
 304
 305    if (cfg != brw->l3.config &&
 306        can_do_pipelined_register_writes(brw->screen)) {
 307       setup_l3_config(brw, cfg);
 308       update_urb_size(brw, cfg);
 309       brw->l3.config = cfg;
 310    }
 311 }