src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "common/gen_l3_config.h"
  25
  26 #include "brw_context.h"
  27 #include "brw_defines.h"
  28 #include "brw_state.h"
  29 #include "intel_batchbuffer.h"
  30
  31 /**
  32  * Calculate the desired L3 partitioning based on the current state of the
  33  * pipeline.  For now this simply returns the conservative defaults calculated
  34  * by get_default_l3_weights(), but we could probably do better by gathering
  35  * more statistics from the pipeline state (e.g. guess of expected URB usage
  36  * and bound surfaces), or by using feed-back from performance counters.
  37  */
  38 static struct gen_l3_weights
  39 get_pipeline_state_l3_weights(const struct brw_context *brw)
  40 {
  41    const struct brw_stage_state *stage_states[] = {
  42       [MESA_SHADER_VERTEX] = &brw->vs.base,
  43       [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
  44       [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
  45       [MESA_SHADER_GEOMETRY] = &brw->gs.base,
  46       [MESA_SHADER_FRAGMENT] = &brw->wm.base,
  47       [MESA_SHADER_COMPUTE] = &brw->cs.base
  48    };
  49    bool needs_dc = false, needs_slm = false;
  50
  51    for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
  52       const struct gl_shader_program *prog =
  53          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
  54       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
  55
  56       needs_dc |= (prog && prog->NumAtomicBuffers) ||
  57          (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
  58       needs_slm |= prog_data && prog_data->total_shared;
  59    }
  60
  61    return gen_get_default_l3_weights(&brw->screen->devinfo,
  62                                      needs_dc, needs_slm);
  63 }
  64
  65 /**
  66  * Program the hardware to use the specified L3 configuration.
  67  */
  68 static void
  69 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
  70 {
  71    const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
  72    const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
  73                        cfg->n[GEN_L3P_ALL];
  74    const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
  75                       cfg->n[GEN_L3P_ALL];
  76    const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
  77                       cfg->n[GEN_L3P_ALL];
  78    const bool has_slm = cfg->n[GEN_L3P_SLM];
  79
  80    /* According to the hardware docs, the L3 partitioning can only be changed
  81     * while the pipeline is completely drained and the caches are flushed,
  82     * which involves a first PIPE_CONTROL flush which stalls the pipeline...
  83     */
  84    brw_emit_pipe_control_flush(brw,
  85                                PIPE_CONTROL_DATA_CACHE_FLUSH |
  86                                PIPE_CONTROL_NO_WRITE |
  87                                PIPE_CONTROL_CS_STALL);
  88
  89    /* ...followed by a second pipelined PIPE_CONTROL that initiates
  90     * invalidation of the relevant caches.  Note that because RO invalidation
  91     * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
  92     * command is processed by the CS) we cannot combine it with the previous
  93     * stalling flush as the hardware documentation suggests, because that
  94     * would cause the CS to stall on previous rendering *after* RO
  95     * invalidation and wouldn't prevent the RO caches from being polluted by
  96     * concurrent rendering before the stall completes.  This intentionally
  97     * doesn't implement the SKL+ hardware workaround suggesting to enable CS
  98     * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
  99     * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
 100     * already guarantee that there is no concurrent GPGPU kernel execution
 101     * (see SKL HSD 2132585).
 102     */
 103    brw_emit_pipe_control_flush(brw,
 104                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 105                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 106                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 107                                PIPE_CONTROL_STATE_CACHE_INVALIDATE |
 108                                PIPE_CONTROL_NO_WRITE);
 109
 110    /* Now send a third stalling flush to make sure that invalidation is
 111     * complete when the L3 configuration registers are modified.
 112     */
 113    brw_emit_pipe_control_flush(brw,
 114                                PIPE_CONTROL_DATA_CACHE_FLUSH |
 115                                PIPE_CONTROL_NO_WRITE |
 116                                PIPE_CONTROL_CS_STALL);
 117
 118    if (brw->gen >= 8) {
 119       assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 120
 121       BEGIN_BATCH(3);
 122       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 123
 124       /* Set up the L3 partitioning. */
 125       OUT_BATCH(GEN8_L3CNTLREG);
 126       OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
 127                 SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
 128                 SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
 129                 SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
 130                 SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 131
 132       ADVANCE_BATCH();
 133
 134    } else {
 135       assert(!cfg->n[GEN_L3P_ALL]);
 136
 137       /* When enabled SLM only uses a portion of the L3 on half of the banks,
 138        * the matching space on the remaining banks has to be allocated to a
 139        * client (URB for all validated configurations) set to the
 140        * lower-bandwidth 2-bank address hashing mode.
 141        */
 142       const bool urb_low_bw = has_slm && !brw->is_baytrail;
 143       assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
 144
 145       /* Minimum number of ways that can be allocated to the URB. */
 146       const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
 147       assert(cfg->n[GEN_L3P_URB] >= n0_urb);
 148
 149       BEGIN_BATCH(7);
 150       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
 151
 152       /* Demote any clients with no ways assigned to LLC. */
 153       OUT_BATCH(GEN7_L3SQCREG1);
 154       OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
 155                  brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
 156                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
 157                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
 158                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
 159                 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
 160                 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
 161
 162       /* Set up the L3 partitioning. */
 163       OUT_BATCH(GEN7_L3CNTLREG2);
 164       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
 165                 SET_FIELD(cfg->n[GEN_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
 166                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
 167                 SET_FIELD(cfg->n[GEN_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
 168                 SET_FIELD(cfg->n[GEN_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
 169                 SET_FIELD(cfg->n[GEN_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
 170       OUT_BATCH(GEN7_L3CNTLREG3);
 171       OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
 172                 SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
 173                 SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 174
 175       ADVANCE_BATCH();
 176
 177       if (brw->is_haswell && brw->screen->cmd_parser_version >= 4) {
 178          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
 179           * them disabled to avoid crashing the system hard.
 180           */
 181          BEGIN_BATCH(5);
 182          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
 183          OUT_BATCH(HSW_SCRATCH1);
 184          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
 185          OUT_BATCH(HSW_ROW_CHICKEN3);
 186          OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
 187                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
 188          ADVANCE_BATCH();
 189       }
 190    }
 191 }
 192
 193 /**
 194  * Update the URB size in the context state for the specified L3
 195  * configuration.
 196  */
 197 static void
 198 update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
 199 {
 200    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 201    const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
 202
 203    if (brw->urb.size != sz) {
 204       brw->urb.size = sz;
 205       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 206    }
 207 }
 208
 209 static void
 210 emit_l3_state(struct brw_context *brw)
 211 {
 212    const struct gen_l3_weights w = get_pipeline_state_l3_weights(brw);
 213    const float dw = gen_diff_l3_weights(w, gen_get_l3_config_weights(brw->l3.config));
 214    /* The distance between any two compatible weight vectors cannot exceed two
 215     * due to the triangle inequality.
 216     */
 217    const float large_dw_threshold = 2.0;
 218    /* Somewhat arbitrary, simply makes sure that there will be no repeated
 219     * transitions to the same L3 configuration, could probably do better here.
 220     */
 221    const float small_dw_threshold = 0.5;
 222    /* If we're emitting a new batch the caches should already be clean and the
 223     * transition should be relatively cheap, so it shouldn't hurt much to use
 224     * the smaller threshold.  Otherwise use the larger threshold so that we
 225     * only reprogram the L3 mid-batch if the most recently programmed
 226     * configuration is incompatible with the current pipeline state.
 227     */
 228    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
 229                                small_dw_threshold : large_dw_threshold);
 230
 231    if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
 232       const struct gen_l3_config *const cfg =
 233          gen_get_l3_config(&brw->screen->devinfo, w);
 234
 235       setup_l3_config(brw, cfg);
 236       update_urb_size(brw, cfg);
 237       brw->l3.config = cfg;
 238
 239       if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
 240          fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
 241          gen_dump_l3_config(cfg, stderr);
 242       }
 243    }
 244 }
 245
 246 const struct brw_tracked_state gen7_l3_state = {
 247    .dirty = {
 248       .mesa = 0,
 249       .brw = BRW_NEW_BATCH |
 250              BRW_NEW_BLORP |
 251              BRW_NEW_CS_PROG_DATA |
 252              BRW_NEW_FS_PROG_DATA |
 253              BRW_NEW_GS_PROG_DATA |
 254              BRW_NEW_VS_PROG_DATA,
 255    },
 256    .emit = emit_l3_state
 257 };
 258
 259 /**
 260  * Hack to restore the default L3 configuration.
 261  *
 262  * This will be called at the end of every batch in order to reset the L3
 263  * configuration to the default values for the time being until the kernel is
 264  * fixed.  Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
 265  * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting
 266  * batch buffers for the default context used by the DDX, which meant that any
 267  * context state changed by the GL would leak into the DDX, the assumption
 268  * being that the DDX would initialize any state it cares about manually.  The
 269  * DDX is however not careful enough to program an L3 configuration
 270  * explicitly, and it makes assumptions about it (URB size) which won't hold
 271  * and cause it to misrender if we let our L3 set-up to leak into the DDX.
 272  *
 273  * Since v4.1 of the Linux kernel the default context is saved and restored
 274  * normally, so it's far less likely for our L3 programming to interfere with
 275  * other contexts -- In fact restoring the default L3 configuration at the end
 276  * of the batch will be redundant most of the time.  A kind of state leak is
 277  * still possible though if the context making assumptions about L3 state is
 278  * created immediately after our context was active (e.g. without the DDX
 279  * default context being scheduled in between) because at present the DRM
 280  * doesn't fully initialize the contents of newly created contexts and instead
 281  * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the
 282  * last active context.
 283  *
 284  * It's possible to realize such a scenario if, say, an X server (or a GL
 285  * application using an outdated non-L3-aware Mesa version) is started while
 286  * another GL application is running and happens to have modified the L3
 287  * configuration, or if no X server is running at all and a GL application
 288  * using a non-L3-aware Mesa version is started after another GL application
 289  * ran and modified the L3 configuration -- The latter situation can actually
 290  * be reproduced easily on IVB in our CI system.
 291  */
 292 void
 293 gen7_restore_default_l3_config(struct brw_context *brw)
 294 {
 295    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 296    const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
 297
 298    if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
 299       setup_l3_config(brw, cfg);
 300       update_urb_size(brw, cfg);
 301       brw->l3.config = cfg;
 302    }
 303 }