src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_defines.h"
  26 #include "brw_state.h"
  27 #include "intel_batchbuffer.h"
  28
  29 /**
  30  * Chunk of L3 cache reserved for some specific purpose.
  31  */
  32 enum brw_l3_partition {
  33    /** Shared local memory. */
  34    L3P_SLM = 0,
  35    /** Unified return buffer. */
  36    L3P_URB,
  37    /** Union of DC and RO. */
  38    L3P_ALL,
  39    /** Data cluster RW partition. */
  40    L3P_DC,
  41    /** Union of IS, C and T. */
  42    L3P_RO,
  43    /** Instruction and state cache. */
  44    L3P_IS,
  45    /** Constant cache. */
  46    L3P_C,
  47    /** Texture cache. */
  48    L3P_T,
  49    /** Number of supported L3 partitions. */
  50    NUM_L3P
  51 };
  52
  53 /**
  54  * L3 configuration represented as the number of ways allocated for each
  55  * partition.  \sa get_l3_way_size().
  56  */
  57 struct brw_l3_config {
  58    unsigned n[NUM_L3P];
  59 };
  60
  61 /**
  62  * IVB/HSW validated L3 configurations.  The first entry will be used as
  63  * default by gen7_restore_default_l3_config(), otherwise the ordering is
  64  * unimportant.
  65  */
  66 static const struct brw_l3_config ivb_l3_configs[] = {
  67    /* SLM URB ALL DC  RO  IS   C   T */
  68    {{  0, 32,  0,  0, 32,  0,  0,  0 }},
  69    {{  0, 32,  0, 16, 16,  0,  0,  0 }},
  70    {{  0, 32,  0,  4,  0,  8,  4, 16 }},
  71    {{  0, 28,  0,  8,  0,  8,  4, 16 }},
  72    {{  0, 28,  0, 16,  0,  8,  4,  8 }},
  73    {{  0, 28,  0,  8,  0, 16,  4,  8 }},
  74    {{  0, 28,  0,  0,  0, 16,  4, 16 }},
  75    {{  0, 32,  0,  0,  0, 16,  0, 16 }},
  76    {{  0, 28,  0,  4, 32,  0,  0,  0 }},
  77    {{ 16, 16,  0, 16, 16,  0,  0,  0 }},
  78    {{ 16, 16,  0,  8,  0,  8,  8,  8 }},
  79    {{ 16, 16,  0,  4,  0,  8,  4, 16 }},
  80    {{ 16, 16,  0,  4,  0, 16,  4,  8 }},
  81    {{ 16, 16,  0,  0, 32,  0,  0,  0 }},
  82    {{ 0 }}
  83 };
  84
  85 /**
  86  * VLV validated L3 configurations.  \sa ivb_l3_configs.
  87  */
  88 static const struct brw_l3_config vlv_l3_configs[] = {
  89    /* SLM URB ALL DC  RO  IS   C   T */
  90    {{  0, 64,  0,  0, 32,  0,  0,  0 }},
  91    {{  0, 80,  0,  0, 16,  0,  0,  0 }},
  92    {{  0, 80,  0,  8,  8,  0,  0,  0 }},
  93    {{  0, 64,  0, 16, 16,  0,  0,  0 }},
  94    {{  0, 60,  0,  4, 32,  0,  0,  0 }},
  95    {{ 32, 32,  0, 16, 16,  0,  0,  0 }},
  96    {{ 32, 40,  0,  8, 16,  0,  0,  0 }},
  97    {{ 32, 40,  0, 16,  8,  0,  0,  0 }},
  98    {{ 0 }}
  99 };
 100
 101 /**
 102  * BDW validated L3 configurations.  \sa ivb_l3_configs.
 103  */
 104 static const struct brw_l3_config bdw_l3_configs[] = {
 105    /* SLM URB ALL DC  RO  IS   C   T */
 106    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 107    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 108    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 109    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 110    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 111    {{ 24, 16, 48,  0,  0,  0,  0,  0 }},
 112    {{ 24, 16,  0, 16, 32,  0,  0,  0 }},
 113    {{ 24, 16,  0, 32, 16,  0,  0,  0 }},
 114    {{ 0 }}
 115 };
 116
 117 /**
 118  * CHV/SKL validated L3 configurations.  \sa ivb_l3_configs.
 119  */
 120 static const struct brw_l3_config chv_l3_configs[] = {
 121    /* SLM URB ALL DC  RO  IS   C   T */
 122    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 123    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 124    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 125    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 126    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 127    {{ 32, 16, 48,  0,  0,  0,  0,  0 }},
 128    {{ 32, 16,  0, 16, 32,  0,  0,  0 }},
 129    {{ 32, 16,  0, 32, 16,  0,  0,  0 }},
 130    {{ 0 }}
 131 };
 132
 133 /**
 134  * Return a zero-terminated array of validated L3 configurations for the
 135  * specified device.
 136  */
 137 static const struct brw_l3_config *
 138 get_l3_configs(const struct brw_device_info *devinfo)
 139 {
 140    switch (devinfo->gen) {
 141    case 7:
 142       return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
 143
 144    case 8:
 145       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 146
 147    case 9:
 148       return chv_l3_configs;
 149
 150    default:
 151       unreachable("Not implemented");
 152    }
 153 }
 154
 155 /**
 156  * Return the size of an L3 way in KB.
 157  */
 158 static unsigned
 159 get_l3_way_size(const struct brw_device_info *devinfo)
 160 {
 161    if (devinfo->is_baytrail)
 162       return 2;
 163
 164    else if (devinfo->is_cherryview || devinfo->gt == 1)
 165       return 4;
 166
 167    else
 168       return 8 * devinfo->num_slices;
 169 }
 170
 171 /**
 172  * L3 configuration represented as a vector of weights giving the desired
 173  * relative size of each partition.  The scale is arbitrary, only the ratios
 174  * between weights will have an influence on the selection of the closest L3
 175  * configuration.
 176  */
 177 struct brw_l3_weights {
 178    float w[NUM_L3P];
 179 };
 180
 181 /**
 182  * L1-normalize a vector of L3 partition weights.
 183  */
 184 static struct brw_l3_weights
 185 norm_l3_weights(struct brw_l3_weights w)
 186 {
 187    float sz = 0;
 188
 189    for (unsigned i = 0; i < NUM_L3P; i++)
 190       sz += w.w[i];
 191
 192    for (unsigned i = 0; i < NUM_L3P; i++)
 193       w.w[i] /= sz;
 194
 195    return w;
 196 }
 197
 198 /**
 199  * Get the relative partition weights of the specified L3 configuration.
 200  */
 201 static struct brw_l3_weights
 202 get_config_l3_weights(const struct brw_l3_config *cfg)
 203 {
 204    if (cfg) {
 205       struct brw_l3_weights w;
 206
 207       for (unsigned i = 0; i < NUM_L3P; i++)
 208          w.w[i] = cfg->n[i];
 209
 210       return norm_l3_weights(w);
 211    } else {
 212       const struct brw_l3_weights w = { { 0 } };
 213       return w;
 214    }
 215 }
 216
 217 /**
 218  * Distance between two L3 configurations represented as vectors of weights.
 219  * Usually just the L1 metric except when the two configurations are
 220  * considered incompatible in which case the distance will be infinite.  Note
 221  * that the compatibility condition is asymmetric -- They will be considered
 222  * incompatible whenever the reference configuration \p w0 requires SLM, DC,
 223  * or URB but \p w1 doesn't provide it.
 224  */
 225 static float
 226 diff_l3_weights(struct brw_l3_weights w0, struct brw_l3_weights w1)
 227 {
 228    if ((w0.w[L3P_SLM] && !w1.w[L3P_SLM]) ||
 229        (w0.w[L3P_DC] && !w1.w[L3P_DC] && !w1.w[L3P_ALL]) ||
 230        (w0.w[L3P_URB] && !w1.w[L3P_URB])) {
 231       return HUGE_VALF;
 232
 233    } else {
 234       float dw = 0;
 235
 236       for (unsigned i = 0; i < NUM_L3P; i++)
 237          dw += fabs(w0.w[i] - w1.w[i]);
 238
 239       return dw;
 240    }
 241 }
 242
 243 /**
 244  * Return the closest validated L3 configuration for the specified device and
 245  * weight vector.
 246  */
 247 static const struct brw_l3_config *
 248 get_l3_config(const struct brw_device_info *devinfo, struct brw_l3_weights w0)
 249 {
 250    const struct brw_l3_config *const cfgs = get_l3_configs(devinfo);
 251    const struct brw_l3_config *cfg_best = NULL;
 252    float dw_best = HUGE_VALF;
 253
 254    for (const struct brw_l3_config *cfg = cfgs; cfg->n[L3P_URB]; cfg++) {
 255       const float dw = diff_l3_weights(w0, get_config_l3_weights(cfg));
 256
 257       if (dw < dw_best) {
 258          cfg_best = cfg;
 259          dw_best = dw;
 260       }
 261    }
 262
 263    return cfg_best;
 264 }
 265
 266 /**
 267  * Return a reasonable default L3 configuration for the specified device based
 268  * on whether SLM and DC are required.  In the non-SLM non-DC case the result
 269  * is intended to approximately resemble the hardware defaults.
 270  */
 271 static struct brw_l3_weights
 272 get_default_l3_weights(const struct brw_device_info *devinfo,
 273                        bool needs_dc, bool needs_slm)
 274 {
 275    struct brw_l3_weights w = {{ 0 }};
 276
 277    w.w[L3P_SLM] = needs_slm;
 278    w.w[L3P_URB] = 1.0;
 279
 280    if (devinfo->gen >= 8) {
 281       w.w[L3P_ALL] = 1.0;
 282    } else {
 283       w.w[L3P_DC] = needs_dc ? 0.1 : 0;
 284       w.w[L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
 285    }
 286
 287    return norm_l3_weights(w);
 288 }
 289
 290 /**
 291  * Calculate the desired L3 partitioning based on the current state of the
 292  * pipeline.  For now this simply returns the conservative defaults calculated
 293  * by get_default_l3_weights(), but we could probably do better by gathering
 294  * more statistics from the pipeline state (e.g. guess of expected URB usage
 295  * and bound surfaces), or by using feed-back from performance counters.
 296  */
 297 static struct brw_l3_weights
 298 get_pipeline_state_l3_weights(const struct brw_context *brw)
 299 {
 300    const struct brw_stage_state *stage_states[] = {
 301       [MESA_SHADER_VERTEX] = &brw->vs.base,
 302       [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
 303       [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
 304       [MESA_SHADER_GEOMETRY] = &brw->gs.base,
 305       [MESA_SHADER_FRAGMENT] = &brw->wm.base,
 306       [MESA_SHADER_COMPUTE] = &brw->cs.base
 307    };
 308    bool needs_dc = false, needs_slm = false;
 309
 310    for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
 311       const struct gl_shader_program *prog =
 312          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
 313       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
 314
 315       needs_dc |= (prog && prog->NumAtomicBuffers) ||
 316          (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
 317       needs_slm |= prog_data && prog_data->total_shared;
 318    }
 319
 320    return get_default_l3_weights(brw->intelScreen->devinfo,
 321                                  needs_dc, needs_slm);
 322 }
 323
 324 /**
 325  * Program the hardware to use the specified L3 configuration.
 326  */
 327 static void
 328 setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
 329 {
 330    const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
 331    const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 332    const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 333    const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 334    const bool has_slm = cfg->n[L3P_SLM];
 335
 336    /* According to the hardware docs, the L3 partitioning can only be changed
 337     * while the pipeline is completely drained and the caches are flushed,
 338     * which involves a first PIPE_CONTROL flush which stalls the pipeline...
 339     */
 340    brw_emit_pipe_control_flush(brw,
 341                                PIPE_CONTROL_DATA_CACHE_FLUSH |
 342                                PIPE_CONTROL_NO_WRITE |
 343                                PIPE_CONTROL_CS_STALL);
 344
 345    /* ...followed by a second pipelined PIPE_CONTROL that initiates
 346     * invalidation of the relevant caches.  Note that because RO invalidation
 347     * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
 348     * command is processed by the CS) we cannot combine it with the previous
 349     * stalling flush as the hardware documentation suggests, because that
 350     * would cause the CS to stall on previous rendering *after* RO
 351     * invalidation and wouldn't prevent the RO caches from being polluted by
 352     * concurrent rendering before the stall completes.  This intentionally
 353     * doesn't implement the SKL+ hardware workaround suggesting to enable CS
 354     * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
 355     * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
 356     * already guarantee that there is no concurrent GPGPU kernel execution
 357     * (see SKL HSD 2132585).
 358     */
 359    brw_emit_pipe_control_flush(brw,
 360                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 361                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 362                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 363                                PIPE_CONTROL_STATE_CACHE_INVALIDATE |
 364                                PIPE_CONTROL_NO_WRITE);
 365
 366    /* Now send a third stalling flush to make sure that invalidation is
 367     * complete when the L3 configuration registers are modified.
 368     */
 369    brw_emit_pipe_control_flush(brw,
 370                                PIPE_CONTROL_DATA_CACHE_FLUSH |
 371                                PIPE_CONTROL_NO_WRITE |
 372                                PIPE_CONTROL_CS_STALL);
 373
 374    if (brw->gen >= 8) {
 375       assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
 376
 377       BEGIN_BATCH(3);
 378       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 379
 380       /* Set up the L3 partitioning. */
 381       OUT_BATCH(GEN8_L3CNTLREG);
 382       OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
 383                 SET_FIELD(cfg->n[L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
 384                 SET_FIELD(cfg->n[L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
 385                 SET_FIELD(cfg->n[L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
 386                 SET_FIELD(cfg->n[L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 387
 388       ADVANCE_BATCH();
 389
 390    } else {
 391       assert(!cfg->n[L3P_ALL]);
 392
 393       /* When enabled SLM only uses a portion of the L3 on half of the banks,
 394        * the matching space on the remaining banks has to be allocated to a
 395        * client (URB for all validated configurations) set to the
 396        * lower-bandwidth 2-bank address hashing mode.
 397        */
 398       const bool urb_low_bw = has_slm && !brw->is_baytrail;
 399       assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
 400
 401       /* Minimum number of ways that can be allocated to the URB. */
 402       const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
 403       assert(cfg->n[L3P_URB] >= n0_urb);
 404
 405       BEGIN_BATCH(7);
 406       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
 407
 408       /* Demote any clients with no ways assigned to LLC. */
 409       OUT_BATCH(GEN7_L3SQCREG1);
 410       OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
 411                  brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
 412                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
 413                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
 414                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
 415                 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
 416                 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
 417
 418       /* Set up the L3 partitioning. */
 419       OUT_BATCH(GEN7_L3CNTLREG2);
 420       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
 421                 SET_FIELD(cfg->n[L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
 422                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
 423                 SET_FIELD(cfg->n[L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
 424                 SET_FIELD(cfg->n[L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
 425                 SET_FIELD(cfg->n[L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
 426       OUT_BATCH(GEN7_L3CNTLREG3);
 427       OUT_BATCH(SET_FIELD(cfg->n[L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
 428                 SET_FIELD(cfg->n[L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
 429                 SET_FIELD(cfg->n[L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 430
 431       ADVANCE_BATCH();
 432
 433       if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) {
 434          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
 435           * them disabled to avoid crashing the system hard.
 436           */
 437          BEGIN_BATCH(5);
 438          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
 439          OUT_BATCH(HSW_SCRATCH1);
 440          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
 441          OUT_BATCH(HSW_ROW_CHICKEN3);
 442          OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
 443                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
 444          ADVANCE_BATCH();
 445       }
 446    }
 447 }
 448
 449 /**
 450  * Return the unit brw_context::urb::size is expressed in, in KB.  \sa
 451  * brw_device_info::urb::size.
 452  */
 453 static unsigned
 454 get_urb_size_scale(const struct brw_device_info *devinfo)
 455 {
 456    return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
 457 }
 458
 459 /**
 460  * Update the URB size in the context state for the specified L3
 461  * configuration.
 462  */
 463 static void
 464 update_urb_size(struct brw_context *brw, const struct brw_l3_config *cfg)
 465 {
 466    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
 467    /* From the SKL "L3 Allocation and Programming" documentation:
 468     *
 469     * "URB is limited to 1008KB due to programming restrictions.  This is not
 470     * a restriction of the L3 implementation, but of the FF and other clients.
 471     * Therefore, in a GT4 implementation it is possible for the programmed
 472     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 473     * only 1008KB of this will be used."
 474     */
 475    const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
 476    const unsigned sz =
 477       MIN2(max, cfg->n[L3P_URB] * get_l3_way_size(devinfo)) /
 478       get_urb_size_scale(devinfo);
 479
 480    if (brw->urb.size != sz) {
 481       brw->urb.size = sz;
 482       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 483    }
 484 }
 485
 486 /**
 487  * Print out the specified L3 configuration.
 488  */
 489 static void
 490 dump_l3_config(const struct brw_l3_config *cfg)
 491 {
 492    fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
 493            cfg->n[L3P_SLM], cfg->n[L3P_URB], cfg->n[L3P_ALL],
 494            cfg->n[L3P_DC], cfg->n[L3P_RO],
 495            cfg->n[L3P_IS], cfg->n[L3P_C], cfg->n[L3P_T]);
 496 }
 497
 498 static void
 499 emit_l3_state(struct brw_context *brw)
 500 {
 501    const struct brw_l3_weights w = get_pipeline_state_l3_weights(brw);
 502    const float dw = diff_l3_weights(w, get_config_l3_weights(brw->l3.config));
 503    /* The distance between any two compatible weight vectors cannot exceed two
 504     * due to the triangle inequality.
 505     */
 506    const float large_dw_threshold = 2.0;
 507    /* Somewhat arbitrary, simply makes sure that there will be no repeated
 508     * transitions to the same L3 configuration, could probably do better here.
 509     */
 510    const float small_dw_threshold = 0.5;
 511    /* If we're emitting a new batch the caches should already be clean and the
 512     * transition should be relatively cheap, so it shouldn't hurt much to use
 513     * the smaller threshold.  Otherwise use the larger threshold so that we
 514     * only reprogram the L3 mid-batch if the most recently programmed
 515     * configuration is incompatible with the current pipeline state.
 516     */
 517    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
 518                                small_dw_threshold : large_dw_threshold);
 519
 520    if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
 521       const struct brw_l3_config *const cfg =
 522          get_l3_config(brw->intelScreen->devinfo, w);
 523
 524       setup_l3_config(brw, cfg);
 525       update_urb_size(brw, cfg);
 526       brw->l3.config = cfg;
 527
 528       if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
 529          fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
 530          dump_l3_config(cfg);
 531       }
 532    }
 533 }
 534
 535 const struct brw_tracked_state gen7_l3_state = {
 536    .dirty = {
 537       .mesa = 0,
 538       .brw = BRW_NEW_BATCH |
 539              BRW_NEW_CS_PROG_DATA |
 540              BRW_NEW_FS_PROG_DATA |
 541              BRW_NEW_GS_PROG_DATA |
 542              BRW_NEW_VS_PROG_DATA,
 543    },
 544    .emit = emit_l3_state
 545 };
 546
 547 /**
 548  * Hack to restore the default L3 configuration.
 549  *
 550  * This will be called at the end of every batch in order to reset the L3
 551  * configuration to the default values for the time being until the kernel is
 552  * fixed.  Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
 553  * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting
 554  * batch buffers for the default context used by the DDX, which meant that any
 555  * context state changed by the GL would leak into the DDX, the assumption
 556  * being that the DDX would initialize any state it cares about manually.  The
 557  * DDX is however not careful enough to program an L3 configuration
 558  * explicitly, and it makes assumptions about it (URB size) which won't hold
 559  * and cause it to misrender if we let our L3 set-up to leak into the DDX.
 560  *
 561  * Since v4.1 of the Linux kernel the default context is saved and restored
 562  * normally, so it's far less likely for our L3 programming to interfere with
 563  * other contexts -- In fact restoring the default L3 configuration at the end
 564  * of the batch will be redundant most of the time.  A kind of state leak is
 565  * still possible though if the context making assumptions about L3 state is
 566  * created immediately after our context was active (e.g. without the DDX
 567  * default context being scheduled in between) because at present the DRM
 568  * doesn't fully initialize the contents of newly created contexts and instead
 569  * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the
 570  * last active context.
 571  *
 572  * It's possible to realize such a scenario if, say, an X server (or a GL
 573  * application using an outdated non-L3-aware Mesa version) is started while
 574  * another GL application is running and happens to have modified the L3
 575  * configuration, or if no X server is running at all and a GL application
 576  * using a non-L3-aware Mesa version is started after another GL application
 577  * ran and modified the L3 configuration -- The latter situation can actually
 578  * be reproduced easily on IVB in our CI system.
 579  */
 580 void
 581 gen7_restore_default_l3_config(struct brw_context *brw)
 582 {
 583    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
 584    /* For efficiency assume that the first entry of the array matches the
 585     * default configuration.
 586     */
 587    const struct brw_l3_config *const cfg = get_l3_configs(devinfo);
 588    assert(cfg == get_l3_config(devinfo,
 589                                get_default_l3_weights(devinfo, false, false)));
 590
 591    if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
 592       setup_l3_config(brw, cfg);
 593       update_urb_size(brw, cfg);
 594       brw->l3.config = cfg;
 595    }
 596 }