src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_defines.h"
  26 #include "brw_state.h"
  27 #include "intel_batchbuffer.h"
  28
  29 /**
  30  * Chunk of L3 cache reserved for some specific purpose.
  31  */
  32 enum brw_l3_partition {
  33    /** Shared local memory. */
  34    L3P_SLM = 0,
  35    /** Unified return buffer. */
  36    L3P_URB,
  37    /** Union of DC and RO. */
  38    L3P_ALL,
  39    /** Data cluster RW partition. */
  40    L3P_DC,
  41    /** Union of IS, C and T. */
  42    L3P_RO,
  43    /** Instruction and state cache. */
  44    L3P_IS,
  45    /** Constant cache. */
  46    L3P_C,
  47    /** Texture cache. */
  48    L3P_T,
  49    /** Number of supported L3 partitions. */
  50    NUM_L3P
  51 };
  52
  53 /**
  54  * L3 configuration represented as the number of ways allocated for each
  55  * partition.  \sa get_l3_way_size().
  56  */
  57 struct brw_l3_config {
  58    unsigned n[NUM_L3P];
  59 };
  60
  61 /**
  62  * IVB/HSW validated L3 configurations.
  63  */
  64 static const struct brw_l3_config ivb_l3_configs[] = {
  65    /* SLM URB ALL DC  RO  IS   C   T */
  66    {{  0, 32,  0,  0, 32,  0,  0,  0 }},
  67    {{  0, 32,  0, 16, 16,  0,  0,  0 }},
  68    {{  0, 32,  0,  4,  0,  8,  4, 16 }},
  69    {{  0, 28,  0,  8,  0,  8,  4, 16 }},
  70    {{  0, 28,  0, 16,  0,  8,  4,  8 }},
  71    {{  0, 28,  0,  8,  0, 16,  4,  8 }},
  72    {{  0, 28,  0,  0,  0, 16,  4, 16 }},
  73    {{  0, 32,  0,  0,  0, 16,  0, 16 }},
  74    {{  0, 28,  0,  4, 32,  0,  0,  0 }},
  75    {{ 16, 16,  0, 16, 16,  0,  0,  0 }},
  76    {{ 16, 16,  0,  8,  0,  8,  8,  8 }},
  77    {{ 16, 16,  0,  4,  0,  8,  4, 16 }},
  78    {{ 16, 16,  0,  4,  0, 16,  4,  8 }},
  79    {{ 16, 16,  0,  0, 32,  0,  0,  0 }},
  80    {{ 0 }}
  81 };
  82
  83 /**
  84  * VLV validated L3 configurations.
  85  */
  86 static const struct brw_l3_config vlv_l3_configs[] = {
  87    /* SLM URB ALL DC  RO  IS   C   T */
  88    {{  0, 64,  0,  0, 32,  0,  0,  0 }},
  89    {{  0, 80,  0,  0, 16,  0,  0,  0 }},
  90    {{  0, 80,  0,  8,  8,  0,  0,  0 }},
  91    {{  0, 64,  0, 16, 16,  0,  0,  0 }},
  92    {{  0, 60,  0,  4, 32,  0,  0,  0 }},
  93    {{ 32, 32,  0, 16, 16,  0,  0,  0 }},
  94    {{ 32, 40,  0,  8, 16,  0,  0,  0 }},
  95    {{ 32, 40,  0, 16,  8,  0,  0,  0 }},
  96    {{ 0 }}
  97 };
  98
  99 /**
 100  * BDW validated L3 configurations.
 101  */
 102 static const struct brw_l3_config bdw_l3_configs[] = {
 103    /* SLM URB ALL DC  RO  IS   C   T */
 104    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 105    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 106    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 107    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 108    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 109    {{ 24, 16, 48,  0,  0,  0,  0,  0 }},
 110    {{ 24, 16,  0, 16, 32,  0,  0,  0 }},
 111    {{ 24, 16,  0, 32, 16,  0,  0,  0 }},
 112    {{ 0 }}
 113 };
 114
 115 /**
 116  * CHV/SKL validated L3 configurations.
 117  */
 118 static const struct brw_l3_config chv_l3_configs[] = {
 119    /* SLM URB ALL DC  RO  IS   C   T */
 120    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 121    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 122    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 123    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 124    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 125    {{ 32, 16, 48,  0,  0,  0,  0,  0 }},
 126    {{ 32, 16,  0, 16, 32,  0,  0,  0 }},
 127    {{ 32, 16,  0, 32, 16,  0,  0,  0 }},
 128    {{ 0 }}
 129 };
 130
 131 /**
 132  * Return a zero-terminated array of validated L3 configurations for the
 133  * specified device.
 134  */
 135 static const struct brw_l3_config *
 136 get_l3_configs(const struct brw_device_info *devinfo)
 137 {
 138    switch (devinfo->gen) {
 139    case 7:
 140       return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
 141
 142    case 8:
 143       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 144
 145    case 9:
 146       return chv_l3_configs;
 147
 148    default:
 149       unreachable("Not implemented");
 150    }
 151 }
 152
 153 /**
 154  * Return the size of an L3 way in KB.
 155  */
 156 static unsigned
 157 get_l3_way_size(const struct brw_device_info *devinfo)
 158 {
 159    if (devinfo->is_baytrail)
 160       return 2;
 161
 162    else if (devinfo->is_cherryview || devinfo->gt == 1)
 163       return 4;
 164
 165    else
 166       return 8 * devinfo->num_slices;
 167 }
 168
 169 /**
 170  * L3 configuration represented as a vector of weights giving the desired
 171  * relative size of each partition.  The scale is arbitrary, only the ratios
 172  * between weights will have an influence on the selection of the closest L3
 173  * configuration.
 174  */
 175 struct brw_l3_weights {
 176    float w[NUM_L3P];
 177 };
 178
 179 /**
 180  * L1-normalize a vector of L3 partition weights.
 181  */
 182 static struct brw_l3_weights
 183 norm_l3_weights(struct brw_l3_weights w)
 184 {
 185    float sz = 0;
 186
 187    for (unsigned i = 0; i < NUM_L3P; i++)
 188       sz += w.w[i];
 189
 190    for (unsigned i = 0; i < NUM_L3P; i++)
 191       w.w[i] /= sz;
 192
 193    return w;
 194 }
 195
 196 /**
 197  * Get the relative partition weights of the specified L3 configuration.
 198  */
 199 static struct brw_l3_weights
 200 get_config_l3_weights(const struct brw_l3_config *cfg)
 201 {
 202    if (cfg) {
 203       struct brw_l3_weights w;
 204
 205       for (unsigned i = 0; i < NUM_L3P; i++)
 206          w.w[i] = cfg->n[i];
 207
 208       return norm_l3_weights(w);
 209    } else {
 210       const struct brw_l3_weights w = { { 0 } };
 211       return w;
 212    }
 213 }
 214
 215 /**
 216  * Distance between two L3 configurations represented as vectors of weights.
 217  * Usually just the L1 metric except when the two configurations are
 218  * considered incompatible in which case the distance will be infinite.  Note
 219  * that the compatibility condition is asymmetric -- They will be considered
 220  * incompatible whenever the reference configuration \p w0 requires SLM, DC,
 221  * or URB but \p w1 doesn't provide it.
 222  */
 223 static float
 224 diff_l3_weights(struct brw_l3_weights w0, struct brw_l3_weights w1)
 225 {
 226    if ((w0.w[L3P_SLM] && !w1.w[L3P_SLM]) ||
 227        (w0.w[L3P_DC] && !w1.w[L3P_DC] && !w1.w[L3P_ALL]) ||
 228        (w0.w[L3P_URB] && !w1.w[L3P_URB])) {
 229       return HUGE_VALF;
 230
 231    } else {
 232       float dw = 0;
 233
 234       for (unsigned i = 0; i < NUM_L3P; i++)
 235          dw += fabs(w0.w[i] - w1.w[i]);
 236
 237       return dw;
 238    }
 239 }
 240
 241 /**
 242  * Return the closest validated L3 configuration for the specified device and
 243  * weight vector.
 244  */
 245 static const struct brw_l3_config *
 246 get_l3_config(const struct brw_device_info *devinfo, struct brw_l3_weights w0)
 247 {
 248    const struct brw_l3_config *const cfgs = get_l3_configs(devinfo);
 249    const struct brw_l3_config *cfg_best = NULL;
 250    float dw_best = HUGE_VALF;
 251
 252    for (const struct brw_l3_config *cfg = cfgs; cfg->n[L3P_URB]; cfg++) {
 253       const float dw = diff_l3_weights(w0, get_config_l3_weights(cfg));
 254
 255       if (dw < dw_best) {
 256          cfg_best = cfg;
 257          dw_best = dw;
 258       }
 259    }
 260
 261    return cfg_best;
 262 }
 263
 264 /**
 265  * Return a reasonable default L3 configuration for the specified device based
 266  * on whether SLM and DC are required.  In the non-SLM non-DC case the result
 267  * is intended to approximately resemble the hardware defaults.
 268  */
 269 static struct brw_l3_weights
 270 get_default_l3_weights(const struct brw_device_info *devinfo,
 271                        bool needs_dc, bool needs_slm)
 272 {
 273    struct brw_l3_weights w = {{ 0 }};
 274
 275    w.w[L3P_SLM] = needs_slm;
 276    w.w[L3P_URB] = 1.0;
 277
 278    if (devinfo->gen >= 8) {
 279       w.w[L3P_ALL] = 1.0;
 280    } else {
 281       w.w[L3P_DC] = needs_dc ? 0.1 : 0;
 282       w.w[L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
 283    }
 284
 285    return norm_l3_weights(w);
 286 }
 287
 288 /**
 289  * Calculate the desired L3 partitioning based on the current state of the
 290  * pipeline.  For now this simply returns the conservative defaults calculated
 291  * by get_default_l3_weights(), but we could probably do better by gathering
 292  * more statistics from the pipeline state (e.g. guess of expected URB usage
 293  * and bound surfaces), or by using feed-back from performance counters.
 294  */
 295 static struct brw_l3_weights
 296 get_pipeline_state_l3_weights(const struct brw_context *brw)
 297 {
 298    const struct brw_stage_state *stage_states[] = {
 299       &brw->vs.base, &brw->gs.base, &brw->wm.base, &brw->cs.base
 300    };
 301    bool needs_dc = false, needs_slm = false;
 302
 303    for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
 304       const struct gl_shader_program *prog =
 305          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
 306       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
 307
 308       needs_dc |= (prog && prog->NumAtomicBuffers) ||
 309          (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
 310       needs_slm |= prog_data && prog_data->total_shared;
 311    }
 312
 313    return get_default_l3_weights(brw->intelScreen->devinfo,
 314                                  needs_dc, needs_slm);
 315 }
 316
 317 /**
 318  * Program the hardware to use the specified L3 configuration.
 319  */
 320 static void
 321 setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
 322 {
 323    const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
 324    const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 325    const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 326    const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
 327    const bool has_slm = cfg->n[L3P_SLM];
 328
 329    /* According to the hardware docs, the L3 partitioning can only be changed
 330     * while the pipeline is completely drained and the caches are flushed,
 331     * which involves a first PIPE_CONTROL flush which stalls the pipeline and
 332     * initiates invalidation of the relevant caches...
 333     */
 334    brw_emit_pipe_control_flush(brw,
 335                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 336                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 337                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 338                                PIPE_CONTROL_DATA_CACHE_INVALIDATE |
 339                                PIPE_CONTROL_NO_WRITE |
 340                                PIPE_CONTROL_CS_STALL);
 341
 342    /* ...followed by a second stalling flush which guarantees that
 343     * invalidation is complete when the L3 configuration registers are
 344     * modified.
 345     */
 346    brw_emit_pipe_control_flush(brw,
 347                                PIPE_CONTROL_DATA_CACHE_INVALIDATE |
 348                                PIPE_CONTROL_NO_WRITE |
 349                                PIPE_CONTROL_CS_STALL);
 350
 351    if (brw->gen >= 8) {
 352       assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
 353
 354       BEGIN_BATCH(3);
 355       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 356
 357       /* Set up the L3 partitioning. */
 358       OUT_BATCH(GEN8_L3CNTLREG);
 359       OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
 360                 SET_FIELD(cfg->n[L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
 361                 SET_FIELD(cfg->n[L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
 362                 SET_FIELD(cfg->n[L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
 363                 SET_FIELD(cfg->n[L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 364
 365       ADVANCE_BATCH();
 366
 367    } else {
 368       assert(!cfg->n[L3P_ALL]);
 369
 370       /* When enabled SLM only uses a portion of the L3 on half of the banks,
 371        * the matching space on the remaining banks has to be allocated to a
 372        * client (URB for all validated configurations) set to the
 373        * lower-bandwidth 2-bank address hashing mode.
 374        */
 375       const bool urb_low_bw = has_slm && !brw->is_baytrail;
 376       assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
 377
 378       /* Minimum number of ways that can be allocated to the URB. */
 379       const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
 380       assert(cfg->n[L3P_URB] >= n0_urb);
 381
 382       BEGIN_BATCH(7);
 383       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
 384
 385       /* Demote any clients with no ways assigned to LLC. */
 386       OUT_BATCH(GEN7_L3SQCREG1);
 387       OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
 388                  brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
 389                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
 390                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
 391                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
 392                 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
 393                 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
 394
 395       /* Set up the L3 partitioning. */
 396       OUT_BATCH(GEN7_L3CNTLREG2);
 397       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
 398                 SET_FIELD(cfg->n[L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
 399                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
 400                 SET_FIELD(cfg->n[L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
 401                 SET_FIELD(cfg->n[L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
 402                 SET_FIELD(cfg->n[L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
 403       OUT_BATCH(GEN7_L3CNTLREG3);
 404       OUT_BATCH(SET_FIELD(cfg->n[L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
 405                 SET_FIELD(cfg->n[L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
 406                 SET_FIELD(cfg->n[L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 407
 408       ADVANCE_BATCH();
 409
 410       if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) {
 411          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
 412           * them disabled to avoid crashing the system hard.
 413           */
 414          BEGIN_BATCH(5);
 415          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
 416          OUT_BATCH(HSW_SCRATCH1);
 417          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
 418          OUT_BATCH(HSW_ROW_CHICKEN3);
 419          OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
 420                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
 421          ADVANCE_BATCH();
 422       }
 423    }
 424 }
 425
 426 /**
 427  * Return the unit brw_context::urb::size is expressed in, in KB.  \sa
 428  * brw_device_info::urb::size.
 429  */
 430 static unsigned
 431 get_urb_size_scale(const struct brw_device_info *devinfo)
 432 {
 433    return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
 434 }
 435
 436 /**
 437  * Update the URB size in the context state for the specified L3
 438  * configuration.
 439  */
 440 static void
 441 update_urb_size(struct brw_context *brw, const struct brw_l3_config *cfg)
 442 {
 443    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
 444    /* From the SKL "L3 Allocation and Programming" documentation:
 445     *
 446     * "URB is limited to 1008KB due to programming restrictions.  This is not
 447     * a restriction of the L3 implementation, but of the FF and other clients.
 448     * Therefore, in a GT4 implementation it is possible for the programmed
 449     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 450     * only 1008KB of this will be used."
 451     */
 452    const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
 453    const unsigned sz =
 454       MIN2(max, cfg->n[L3P_URB] * get_l3_way_size(devinfo)) /
 455       get_urb_size_scale(devinfo);
 456
 457    if (brw->urb.size != sz) {
 458       brw->urb.size = sz;
 459       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 460    }
 461 }
 462
 463 static void
 464 emit_l3_state(struct brw_context *brw)
 465 {
 466    const struct brw_l3_weights w = get_pipeline_state_l3_weights(brw);
 467    const float dw = diff_l3_weights(w, get_config_l3_weights(brw->l3.config));
 468    /* The distance between any two compatible weight vectors cannot exceed two
 469     * due to the triangle inequality.
 470     */
 471    const float large_dw_threshold = 2.0;
 472    /* Somewhat arbitrary, simply makes sure that there will be no repeated
 473     * transitions to the same L3 configuration, could probably do better here.
 474     */
 475    const float small_dw_threshold = 0.5;
 476    /* If we're emitting a new batch the caches should already be clean and the
 477     * transition should be relatively cheap, so it shouldn't hurt much to use
 478     * the smaller threshold.  Otherwise use the larger threshold so that we
 479     * only reprogram the L3 mid-batch if the most recently programmed
 480     * configuration is incompatible with the current pipeline state.
 481     */
 482    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
 483                                small_dw_threshold : large_dw_threshold);
 484
 485    if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
 486       const struct brw_l3_config *const cfg =
 487          get_l3_config(brw->intelScreen->devinfo, w);
 488
 489       setup_l3_config(brw, cfg);
 490       update_urb_size(brw, cfg);
 491       brw->l3.config = cfg;
 492    }
 493 }
 494
 495 const struct brw_tracked_state gen7_l3_state = {
 496    .dirty = {
 497       .mesa = 0,
 498       .brw = BRW_NEW_BATCH |
 499              BRW_NEW_CS_PROG_DATA |
 500              BRW_NEW_FS_PROG_DATA |
 501              BRW_NEW_GS_PROG_DATA |
 502              BRW_NEW_VS_PROG_DATA,
 503    },
 504    .emit = emit_l3_state
 505 };