2 * Copyright (c) 2015 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "brw_context.h"
25 #include "brw_defines.h"
26 #include "brw_state.h"
27 #include "intel_batchbuffer.h"
30 * Chunk of L3 cache reserved for some specific purpose.
32 enum brw_l3_partition
{
33 /** Shared local memory. */
35 /** Unified return buffer. */
37 /** Union of DC and RO. */
39 /** Data cluster RW partition. */
41 /** Union of IS, C and T. */
43 /** Instruction and state cache. */
45 /** Constant cache. */
49 /** Number of supported L3 partitions. */
54 * L3 configuration represented as the number of ways allocated for each
55 * partition. \sa get_l3_way_size().
57 struct brw_l3_config
{
62 * IVB/HSW validated L3 configurations.
64 static const struct brw_l3_config ivb_l3_configs
[] = {
65 /* SLM URB ALL DC RO IS C T */
66 {{ 0, 32, 0, 0, 32, 0, 0, 0 }},
67 {{ 0, 32, 0, 16, 16, 0, 0, 0 }},
68 {{ 0, 32, 0, 4, 0, 8, 4, 16 }},
69 {{ 0, 28, 0, 8, 0, 8, 4, 16 }},
70 {{ 0, 28, 0, 16, 0, 8, 4, 8 }},
71 {{ 0, 28, 0, 8, 0, 16, 4, 8 }},
72 {{ 0, 28, 0, 0, 0, 16, 4, 16 }},
73 {{ 0, 32, 0, 0, 0, 16, 0, 16 }},
74 {{ 0, 28, 0, 4, 32, 0, 0, 0 }},
75 {{ 16, 16, 0, 16, 16, 0, 0, 0 }},
76 {{ 16, 16, 0, 8, 0, 8, 8, 8 }},
77 {{ 16, 16, 0, 4, 0, 8, 4, 16 }},
78 {{ 16, 16, 0, 4, 0, 16, 4, 8 }},
79 {{ 16, 16, 0, 0, 32, 0, 0, 0 }},
84 * VLV validated L3 configurations.
86 static const struct brw_l3_config vlv_l3_configs
[] = {
87 /* SLM URB ALL DC RO IS C T */
88 {{ 0, 64, 0, 0, 32, 0, 0, 0 }},
89 {{ 0, 80, 0, 0, 16, 0, 0, 0 }},
90 {{ 0, 80, 0, 8, 8, 0, 0, 0 }},
91 {{ 0, 64, 0, 16, 16, 0, 0, 0 }},
92 {{ 0, 60, 0, 4, 32, 0, 0, 0 }},
93 {{ 32, 32, 0, 16, 16, 0, 0, 0 }},
94 {{ 32, 40, 0, 8, 16, 0, 0, 0 }},
95 {{ 32, 40, 0, 16, 8, 0, 0, 0 }},
100 * BDW validated L3 configurations.
102 static const struct brw_l3_config bdw_l3_configs
[] = {
103 /* SLM URB ALL DC RO IS C T */
104 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
105 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
106 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
107 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
108 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
109 {{ 24, 16, 48, 0, 0, 0, 0, 0 }},
110 {{ 24, 16, 0, 16, 32, 0, 0, 0 }},
111 {{ 24, 16, 0, 32, 16, 0, 0, 0 }},
116 * CHV/SKL validated L3 configurations.
118 static const struct brw_l3_config chv_l3_configs
[] = {
119 /* SLM URB ALL DC RO IS C T */
120 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
121 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
122 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
123 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
124 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
125 {{ 32, 16, 48, 0, 0, 0, 0, 0 }},
126 {{ 32, 16, 0, 16, 32, 0, 0, 0 }},
127 {{ 32, 16, 0, 32, 16, 0, 0, 0 }},
132 * Return a zero-terminated array of validated L3 configurations for the
135 static const struct brw_l3_config
*
136 get_l3_configs(const struct brw_device_info
*devinfo
)
138 switch (devinfo
->gen
) {
140 return (devinfo
->is_baytrail
? vlv_l3_configs
: ivb_l3_configs
);
143 return (devinfo
->is_cherryview
? chv_l3_configs
: bdw_l3_configs
);
146 return chv_l3_configs
;
149 unreachable("Not implemented");
154 * Return the size of an L3 way in KB.
157 get_l3_way_size(const struct brw_device_info
*devinfo
)
159 if (devinfo
->is_baytrail
)
162 else if (devinfo
->is_cherryview
|| devinfo
->gt
== 1)
166 return 8 * devinfo
->num_slices
;
170 * L3 configuration represented as a vector of weights giving the desired
171 * relative size of each partition. The scale is arbitrary, only the ratios
172 * between weights will have an influence on the selection of the closest L3
175 struct brw_l3_weights
{
180 * L1-normalize a vector of L3 partition weights.
182 static struct brw_l3_weights
183 norm_l3_weights(struct brw_l3_weights w
)
187 for (unsigned i
= 0; i
< NUM_L3P
; i
++)
190 for (unsigned i
= 0; i
< NUM_L3P
; i
++)
197 * Get the relative partition weights of the specified L3 configuration.
199 static struct brw_l3_weights
200 get_config_l3_weights(const struct brw_l3_config
*cfg
)
203 struct brw_l3_weights w
;
205 for (unsigned i
= 0; i
< NUM_L3P
; i
++)
208 return norm_l3_weights(w
);
210 const struct brw_l3_weights w
= { { 0 } };
216 * Distance between two L3 configurations represented as vectors of weights.
217 * Usually just the L1 metric except when the two configurations are
218 * considered incompatible in which case the distance will be infinite. Note
219 * that the compatibility condition is asymmetric -- They will be considered
220 * incompatible whenever the reference configuration \p w0 requires SLM, DC,
221 * or URB but \p w1 doesn't provide it.
224 diff_l3_weights(struct brw_l3_weights w0
, struct brw_l3_weights w1
)
226 if ((w0
.w
[L3P_SLM
] && !w1
.w
[L3P_SLM
]) ||
227 (w0
.w
[L3P_DC
] && !w1
.w
[L3P_DC
] && !w1
.w
[L3P_ALL
]) ||
228 (w0
.w
[L3P_URB
] && !w1
.w
[L3P_URB
])) {
234 for (unsigned i
= 0; i
< NUM_L3P
; i
++)
235 dw
+= fabs(w0
.w
[i
] - w1
.w
[i
]);
242 * Return the closest validated L3 configuration for the specified device and
245 static const struct brw_l3_config
*
246 get_l3_config(const struct brw_device_info
*devinfo
, struct brw_l3_weights w0
)
248 const struct brw_l3_config
*const cfgs
= get_l3_configs(devinfo
);
249 const struct brw_l3_config
*cfg_best
= NULL
;
250 float dw_best
= HUGE_VALF
;
252 for (const struct brw_l3_config
*cfg
= cfgs
; cfg
->n
[L3P_URB
]; cfg
++) {
253 const float dw
= diff_l3_weights(w0
, get_config_l3_weights(cfg
));
265 * Return a reasonable default L3 configuration for the specified device based
266 * on whether SLM and DC are required. In the non-SLM non-DC case the result
267 * is intended to approximately resemble the hardware defaults.
269 static struct brw_l3_weights
270 get_default_l3_weights(const struct brw_device_info
*devinfo
,
271 bool needs_dc
, bool needs_slm
)
273 struct brw_l3_weights w
= {{ 0 }};
275 w
.w
[L3P_SLM
] = needs_slm
;
278 if (devinfo
->gen
>= 8) {
281 w
.w
[L3P_DC
] = needs_dc
? 0.1 : 0;
282 w
.w
[L3P_RO
] = devinfo
->is_baytrail
? 0.5 : 1.0;
285 return norm_l3_weights(w
);
289 * Calculate the desired L3 partitioning based on the current state of the
290 * pipeline. For now this simply returns the conservative defaults calculated
291 * by get_default_l3_weights(), but we could probably do better by gathering
292 * more statistics from the pipeline state (e.g. guess of expected URB usage
293 * and bound surfaces), or by using feed-back from performance counters.
295 static struct brw_l3_weights
296 get_pipeline_state_l3_weights(const struct brw_context
*brw
)
298 const struct brw_stage_state
*stage_states
[] = {
299 &brw
->vs
.base
, &brw
->gs
.base
, &brw
->wm
.base
, &brw
->cs
.base
301 bool needs_dc
= false, needs_slm
= false;
303 for (unsigned i
= 0; i
< ARRAY_SIZE(stage_states
); i
++) {
304 const struct gl_shader_program
*prog
=
305 brw
->ctx
._Shader
->CurrentProgram
[stage_states
[i
]->stage
];
306 const struct brw_stage_prog_data
*prog_data
= stage_states
[i
]->prog_data
;
308 needs_dc
|= (prog
&& prog
->NumAtomicBuffers
) ||
309 (prog_data
&& (prog_data
->total_scratch
|| prog_data
->nr_image_params
));
310 needs_slm
|= prog_data
&& prog_data
->total_shared
;
313 return get_default_l3_weights(brw
->intelScreen
->devinfo
,
314 needs_dc
, needs_slm
);
318 * Program the hardware to use the specified L3 configuration.
321 setup_l3_config(struct brw_context
*brw
, const struct brw_l3_config
*cfg
)
323 const bool has_dc
= cfg
->n
[L3P_DC
] || cfg
->n
[L3P_ALL
];
324 const bool has_is
= cfg
->n
[L3P_IS
] || cfg
->n
[L3P_RO
] || cfg
->n
[L3P_ALL
];
325 const bool has_c
= cfg
->n
[L3P_C
] || cfg
->n
[L3P_RO
] || cfg
->n
[L3P_ALL
];
326 const bool has_t
= cfg
->n
[L3P_T
] || cfg
->n
[L3P_RO
] || cfg
->n
[L3P_ALL
];
327 const bool has_slm
= cfg
->n
[L3P_SLM
];
329 /* According to the hardware docs, the L3 partitioning can only be changed
330 * while the pipeline is completely drained and the caches are flushed,
331 * which involves a first PIPE_CONTROL flush which stalls the pipeline and
332 * initiates invalidation of the relevant caches...
334 brw_emit_pipe_control_flush(brw
,
335 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
336 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
337 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
338 PIPE_CONTROL_DATA_CACHE_INVALIDATE
|
339 PIPE_CONTROL_NO_WRITE
|
340 PIPE_CONTROL_CS_STALL
);
342 /* ...followed by a second stalling flush which guarantees that
343 * invalidation is complete when the L3 configuration registers are
346 brw_emit_pipe_control_flush(brw
,
347 PIPE_CONTROL_DATA_CACHE_INVALIDATE
|
348 PIPE_CONTROL_NO_WRITE
|
349 PIPE_CONTROL_CS_STALL
);
352 assert(!cfg
->n
[L3P_IS
] && !cfg
->n
[L3P_C
] && !cfg
->n
[L3P_T
]);
355 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
357 /* Set up the L3 partitioning. */
358 OUT_BATCH(GEN8_L3CNTLREG
);
359 OUT_BATCH((has_slm
? GEN8_L3CNTLREG_SLM_ENABLE
: 0) |
360 SET_FIELD(cfg
->n
[L3P_URB
], GEN8_L3CNTLREG_URB_ALLOC
) |
361 SET_FIELD(cfg
->n
[L3P_RO
], GEN8_L3CNTLREG_RO_ALLOC
) |
362 SET_FIELD(cfg
->n
[L3P_DC
], GEN8_L3CNTLREG_DC_ALLOC
) |
363 SET_FIELD(cfg
->n
[L3P_ALL
], GEN8_L3CNTLREG_ALL_ALLOC
));
368 assert(!cfg
->n
[L3P_ALL
]);
370 /* When enabled SLM only uses a portion of the L3 on half of the banks,
371 * the matching space on the remaining banks has to be allocated to a
372 * client (URB for all validated configurations) set to the
373 * lower-bandwidth 2-bank address hashing mode.
375 const bool urb_low_bw
= has_slm
&& !brw
->is_baytrail
;
376 assert(!urb_low_bw
|| cfg
->n
[L3P_URB
] == cfg
->n
[L3P_SLM
]);
378 /* Minimum number of ways that can be allocated to the URB. */
379 const unsigned n0_urb
= (brw
->is_baytrail
? 32 : 0);
380 assert(cfg
->n
[L3P_URB
] >= n0_urb
);
383 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (7 - 2));
385 /* Demote any clients with no ways assigned to LLC. */
386 OUT_BATCH(GEN7_L3SQCREG1
);
387 OUT_BATCH((brw
->is_haswell
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
388 brw
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
389 IVB_L3SQCREG1_SQGHPCI_DEFAULT
) |
390 (has_dc
? 0 : GEN7_L3SQCREG1_CONV_DC_UC
) |
391 (has_is
? 0 : GEN7_L3SQCREG1_CONV_IS_UC
) |
392 (has_c
? 0 : GEN7_L3SQCREG1_CONV_C_UC
) |
393 (has_t
? 0 : GEN7_L3SQCREG1_CONV_T_UC
));
395 /* Set up the L3 partitioning. */
396 OUT_BATCH(GEN7_L3CNTLREG2
);
397 OUT_BATCH((has_slm
? GEN7_L3CNTLREG2_SLM_ENABLE
: 0) |
398 SET_FIELD(cfg
->n
[L3P_URB
] - n0_urb
, GEN7_L3CNTLREG2_URB_ALLOC
) |
399 (urb_low_bw
? GEN7_L3CNTLREG2_URB_LOW_BW
: 0) |
400 SET_FIELD(cfg
->n
[L3P_ALL
], GEN7_L3CNTLREG2_ALL_ALLOC
) |
401 SET_FIELD(cfg
->n
[L3P_RO
], GEN7_L3CNTLREG2_RO_ALLOC
) |
402 SET_FIELD(cfg
->n
[L3P_DC
], GEN7_L3CNTLREG2_DC_ALLOC
));
403 OUT_BATCH(GEN7_L3CNTLREG3
);
404 OUT_BATCH(SET_FIELD(cfg
->n
[L3P_IS
], GEN7_L3CNTLREG3_IS_ALLOC
) |
405 SET_FIELD(cfg
->n
[L3P_C
], GEN7_L3CNTLREG3_C_ALLOC
) |
406 SET_FIELD(cfg
->n
[L3P_T
], GEN7_L3CNTLREG3_T_ALLOC
));
410 if (brw
->is_haswell
&& brw
->intelScreen
->cmd_parser_version
>= 4) {
411 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
412 * them disabled to avoid crashing the system hard.
415 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
416 OUT_BATCH(HSW_SCRATCH1
);
417 OUT_BATCH(has_dc
? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE
);
418 OUT_BATCH(HSW_ROW_CHICKEN3
);
419 OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE
) |
420 (has_dc
? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE
));