src/mesa/drivers/dri/i965/gen7_l3_state.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_defines.h"
  26 #include "brw_state.h"
  27 #include "intel_batchbuffer.h"
  28
  29 /**
  30  * Chunk of L3 cache reserved for some specific purpose.
  31  */
  32 enum brw_l3_partition {
  33    /** Shared local memory. */
  34    L3P_SLM = 0,
  35    /** Unified return buffer. */
  36    L3P_URB,
  37    /** Union of DC and RO. */
  38    L3P_ALL,
  39    /** Data cluster RW partition. */
  40    L3P_DC,
  41    /** Union of IS, C and T. */
  42    L3P_RO,
  43    /** Instruction and state cache. */
  44    L3P_IS,
  45    /** Constant cache. */
  46    L3P_C,
  47    /** Texture cache. */
  48    L3P_T,
  49    /** Number of supported L3 partitions. */
  50    NUM_L3P
  51 };
  52
  53 /**
  54  * L3 configuration represented as the number of ways allocated for each
  55  * partition.  \sa get_l3_way_size().
  56  */
  57 struct brw_l3_config {
  58    unsigned n[NUM_L3P];
  59 };
  60
  61 /**
  62  * IVB/HSW validated L3 configurations.
  63  */
  64 static const struct brw_l3_config ivb_l3_configs[] = {
  65    /* SLM URB ALL DC  RO  IS   C   T */
  66    {{  0, 32,  0,  0, 32,  0,  0,  0 }},
  67    {{  0, 32,  0, 16, 16,  0,  0,  0 }},
  68    {{  0, 32,  0,  4,  0,  8,  4, 16 }},
  69    {{  0, 28,  0,  8,  0,  8,  4, 16 }},
  70    {{  0, 28,  0, 16,  0,  8,  4,  8 }},
  71    {{  0, 28,  0,  8,  0, 16,  4,  8 }},
  72    {{  0, 28,  0,  0,  0, 16,  4, 16 }},
  73    {{  0, 32,  0,  0,  0, 16,  0, 16 }},
  74    {{  0, 28,  0,  4, 32,  0,  0,  0 }},
  75    {{ 16, 16,  0, 16, 16,  0,  0,  0 }},
  76    {{ 16, 16,  0,  8,  0,  8,  8,  8 }},
  77    {{ 16, 16,  0,  4,  0,  8,  4, 16 }},
  78    {{ 16, 16,  0,  4,  0, 16,  4,  8 }},
  79    {{ 16, 16,  0,  0, 32,  0,  0,  0 }},
  80    {{ 0 }}
  81 };
  82
  83 /**
  84  * VLV validated L3 configurations.
  85  */
  86 static const struct brw_l3_config vlv_l3_configs[] = {
  87    /* SLM URB ALL DC  RO  IS   C   T */
  88    {{  0, 64,  0,  0, 32,  0,  0,  0 }},
  89    {{  0, 80,  0,  0, 16,  0,  0,  0 }},
  90    {{  0, 80,  0,  8,  8,  0,  0,  0 }},
  91    {{  0, 64,  0, 16, 16,  0,  0,  0 }},
  92    {{  0, 60,  0,  4, 32,  0,  0,  0 }},
  93    {{ 32, 32,  0, 16, 16,  0,  0,  0 }},
  94    {{ 32, 40,  0,  8, 16,  0,  0,  0 }},
  95    {{ 32, 40,  0, 16,  8,  0,  0,  0 }},
  96    {{ 0 }}
  97 };
  98
  99 /**
 100  * BDW validated L3 configurations.
 101  */
 102 static const struct brw_l3_config bdw_l3_configs[] = {
 103    /* SLM URB ALL DC  RO  IS   C   T */
 104    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 105    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 106    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 107    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 108    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 109    {{ 24, 16, 48,  0,  0,  0,  0,  0 }},
 110    {{ 24, 16,  0, 16, 32,  0,  0,  0 }},
 111    {{ 24, 16,  0, 32, 16,  0,  0,  0 }},
 112    {{ 0 }}
 113 };
 114
 115 /**
 116  * CHV/SKL validated L3 configurations.
 117  */
 118 static const struct brw_l3_config chv_l3_configs[] = {
 119    /* SLM URB ALL DC  RO  IS   C   T */
 120    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 121    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 122    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 123    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 124    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 125    {{ 32, 16, 48,  0,  0,  0,  0,  0 }},
 126    {{ 32, 16,  0, 16, 32,  0,  0,  0 }},
 127    {{ 32, 16,  0, 32, 16,  0,  0,  0 }},
 128    {{ 0 }}
 129 };
 130
 131 /**
 132  * Return a zero-terminated array of validated L3 configurations for the
 133  * specified device.
 134  */
 135 static const struct brw_l3_config *
 136 get_l3_configs(const struct brw_device_info *devinfo)
 137 {
 138    switch (devinfo->gen) {
 139    case 7:
 140       return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
 141
 142    case 8:
 143       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 144
 145    case 9:
 146       return chv_l3_configs;
 147
 148    default:
 149       unreachable("Not implemented");
 150    }
 151 }
 152
 153 /**
 154  * Return the size of an L3 way in KB.
 155  */
 156 static unsigned
 157 get_l3_way_size(const struct brw_device_info *devinfo)
 158 {
 159    if (devinfo->is_baytrail)
 160       return 2;
 161
 162    else if (devinfo->is_cherryview || devinfo->gt == 1)
 163       return 4;
 164
 165    else
 166       return 8 * devinfo->num_slices;
 167 }