src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_regions.h"
  26 #include "intel_fbo.h"
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30
  31 unsigned int
  32 gen7_depth_format(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct gl_framebuffer *fb = ctx->DrawBuffer;
  37    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  38    struct intel_region *region = NULL;
  39
  40    if (drb)
  41       region = drb->region;
  42    else
  43       return BRW_DEPTHFORMAT_D32_FLOAT;
  44
  45    switch (region->cpp) {
  46    case 2:
  47       return BRW_DEPTHFORMAT_D16_UNORM;
  48    case 4:
  49       if (intel->depth_buffer_is_float)
  50          return BRW_DEPTHFORMAT_D32_FLOAT;
  51       else
  52          return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
  53    default:
  54       assert(!"Should not get here.");
  55    }
  56    return 0;
  57 }
  58
  59 static void emit_depthbuffer(struct brw_context *brw)
  60 {
  61    struct intel_context *intel = &brw->intel;
  62    struct gl_context *ctx = &intel->ctx;
  63    struct gl_framebuffer *fb = ctx->DrawBuffer;
  64    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  65    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  66    struct intel_region *region = NULL;
  67
  68    /* _NEW_BUFFERS */
  69    if (drb)
  70       region = drb->region;
  71    else if (srb)
  72       region = srb->region;
  73
  74    if (region == NULL) {
  75       BEGIN_BATCH(7);
  76       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  77       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
  78                 (BRW_SURFACE_NULL << 29));
  79       OUT_BATCH(0);
  80       OUT_BATCH(0);
  81       OUT_BATCH(0);
  82       OUT_BATCH(0);
  83       OUT_BATCH(0);
  84       ADVANCE_BATCH();
  85    } else {
  86       uint32_t tile_x, tile_y, offset;
  87
  88       offset = intel_region_tile_offsets(region, &tile_x, &tile_y);
  89
  90       assert(region->tiling == I915_TILING_Y);
  91
  92       /* _NEW_DEPTH */
  93       BEGIN_BATCH(7);
  94       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  95       OUT_BATCH(((region->pitch * region->cpp) - 1) |
  96                 (gen7_depth_format(brw) << 18) |
  97                 (0 << 22) /* no HiZ buffer */ |
  98                 (0 << 27) /* no stencil write */ |
  99                 ((ctx->Depth.Mask != 0) << 28) |
 100                 (BRW_SURFACE_2D << 29));
 101       OUT_RELOC(region->buffer,
 102                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 103                 offset);
 104       OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
 105       OUT_BATCH(0);
 106       OUT_BATCH(tile_x | (tile_y << 16));
 107       OUT_BATCH(0);
 108       ADVANCE_BATCH();
 109    }
 110
 111    BEGIN_BATCH(4);
 112    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
 113    OUT_BATCH(0);
 114    OUT_BATCH(0);
 115    OUT_BATCH(0);
 116    ADVANCE_BATCH();
 117
 118    BEGIN_BATCH(4);
 119    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (4 - 2));
 120    OUT_BATCH(0);
 121    OUT_BATCH(0);
 122    OUT_BATCH(0);
 123    ADVANCE_BATCH();
 124
 125    BEGIN_BATCH(3);
 126    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 127    OUT_BATCH(0);
 128    OUT_BATCH(0);
 129    ADVANCE_BATCH();
 130 }
 131
 132 /**
 133  * \see brw_context.state.depth_region
 134  */
 135 const struct brw_tracked_state gen7_depthbuffer = {
 136    .dirty = {
 137       .mesa = (_NEW_BUFFERS | _NEW_DEPTH),
 138       .brw = BRW_NEW_BATCH,
 139       .cache = 0,
 140    },
 141    .emit = emit_depthbuffer,
 142 };