src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31
  32 void
  33 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
  34                             struct intel_mipmap_tree *depth_mt,
  35                             uint32_t depth_offset, uint32_t depthbuffer_format,
  36                             uint32_t depth_surface_type,
  37                             struct intel_mipmap_tree *stencil_mt,
  38                             bool hiz, bool separate_stencil,
  39                             uint32_t width, uint32_t height,
  40                             uint32_t tile_x, uint32_t tile_y)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct gl_context *ctx = &intel->ctx;
  44
  45    intel_emit_depth_stall_flushes(brw);
  46
  47    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
  48    BEGIN_BATCH(7);
  49    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  50    OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
  51              (depthbuffer_format << 18) |
  52              ((hiz ? 1 : 0) << 22) |
  53              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
  54              ((ctx->Depth.Mask != 0) << 28) |
  55              (depth_surface_type << 29));
  56
  57    if (depth_mt) {
  58       OUT_RELOC(depth_mt->region->bo,
  59                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  60                 depth_offset);
  61    } else {
  62       OUT_BATCH(0);
  63    }
  64
  65    OUT_BATCH(((width + tile_x - 1) << 4) |
  66              ((height + tile_y - 1) << 18));
  67    OUT_BATCH(0);
  68    OUT_BATCH(tile_x | (tile_y << 16));
  69    OUT_BATCH(0);
  70    ADVANCE_BATCH();
  71
  72    if (!hiz) {
  73       BEGIN_BATCH(3);
  74       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  75       OUT_BATCH(0);
  76       OUT_BATCH(0);
  77       ADVANCE_BATCH();
  78    } else {
  79       struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
  80       BEGIN_BATCH(3);
  81       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  82       OUT_BATCH(hiz_mt->region->pitch - 1);
  83       OUT_RELOC(hiz_mt->region->bo,
  84                 I915_GEM_DOMAIN_RENDER,
  85                 I915_GEM_DOMAIN_RENDER,
  86                 brw->depthstencil.hiz_offset);
  87       ADVANCE_BATCH();
  88    }
  89
  90    if (stencil_mt == NULL) {
  91       BEGIN_BATCH(3);
  92       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95       ADVANCE_BATCH();
  96    } else {
  97       const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0;
  98
  99       BEGIN_BATCH(3);
 100       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 101       /* The stencil buffer has quirky pitch requirements.  From the Graphics
 102        * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
 103        * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
 104        * field "Surface Pitch":
 105        *
 106        *    The pitch must be set to 2x the value computed based on width, as
 107        *    the stencil buffer is stored with two rows interleaved.
 108        *
 109        * (Note that it is not 100% clear whether this intended to apply to
 110        * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
 111        * imply that it doesn't), however the comment appears on a "DevIVB+"
 112        * page (which would imply that it does).  Experiments with the hardware
 113        * indicate that it does.
 114        */
 115       OUT_BATCH(enabled |
 116                 (2 * stencil_mt->region->pitch - 1));
 117       OUT_RELOC(stencil_mt->region->bo,
 118                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 119                 brw->depthstencil.stencil_offset);
 120       ADVANCE_BATCH();
 121    }
 122
 123    BEGIN_BATCH(3);
 124    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 125    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 126    OUT_BATCH(1);
 127    ADVANCE_BATCH();
 128 }
 129
 130 /**
 131  * \see brw_context.state.depth_region
 132  */
 133 const struct brw_tracked_state gen7_depthbuffer = {
 134    .dirty = {
 135       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 136       .brw = BRW_NEW_BATCH,
 137       .cache = 0,
 138    },
 139    .emit = brw_emit_depthbuffer,
 140 };