src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31
  32 static void emit_depthbuffer(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct gl_framebuffer *fb = ctx->DrawBuffer;
  37
  38    /* _NEW_BUFFERS */
  39    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  40    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  41    struct intel_mipmap_tree *depth_mt = NULL,
  42                             *stencil_mt = NULL,
  43                             *hiz_mt = NULL;
  44
  45    if (drb)
  46       depth_mt = drb->mt;
  47
  48    if (depth_mt)
  49       hiz_mt = depth_mt->hiz_mt;
  50
  51    if (srb) {
  52       stencil_mt = srb->mt;
  53       if (stencil_mt->stencil_mt)
  54          stencil_mt = stencil_mt->stencil_mt;
  55
  56       assert(stencil_mt->format == MESA_FORMAT_S8);
  57    }
  58
  59    /* Gen7 doesn't support packed depth/stencil */
  60    assert(stencil_mt == NULL || depth_mt != stencil_mt);
  61    assert(!depth_mt || !_mesa_is_format_packed_depth_stencil(depth_mt->format));
  62
  63    intel_emit_depth_stall_flushes(intel);
  64
  65    if (depth_mt == NULL) {
  66       uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
  67       uint32_t dw3 = 0;
  68
  69       if (stencil_mt == NULL) {
  70          dw1 |= (BRW_SURFACE_NULL << 29);
  71       } else {
  72          struct intel_region *region = stencil_mt->region;
  73
  74          /* _NEW_STENCIL: enable stencil buffer writes */
  75          dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
  76
  77          /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
  78          dw1 |= (BRW_SURFACE_2D << 29);
  79          dw3 = ((srb->Base.Width - 1) << 4) |
  80                ((srb->Base.Height - 1) << 18);
  81       }
  82
  83       BEGIN_BATCH(7);
  84       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  85       OUT_BATCH(dw1);
  86       OUT_BATCH(0);
  87       OUT_BATCH(dw3);
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90       OUT_BATCH(0);
  91       ADVANCE_BATCH();
  92    } else {
  93       struct intel_region *region = depth_mt->region;
  94       uint32_t tile_x, tile_y, offset;
  95
  96       offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
  97
  98       assert(region->tiling == I915_TILING_Y);
  99
 100       /* _NEW_DEPTH, _NEW_STENCIL */
 101       BEGIN_BATCH(7);
 102       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 103       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 104                 (brw_depthbuffer_format(brw) << 18) |
 105                 ((hiz_mt ? 1 : 0) << 22) | /* hiz enable */
 106                 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
 107                 ((ctx->Depth.Mask != 0) << 28) |
 108                 (BRW_SURFACE_2D << 29));
 109       OUT_RELOC(region->bo,
 110                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 111                 offset);
 112       OUT_BATCH(((drb->Base.Width - 1) << 4) |
 113                 ((drb->Base.Height - 1) << 18));
 114       OUT_BATCH(0);
 115       OUT_BATCH(tile_x | (tile_y << 16));
 116       OUT_BATCH(0);
 117       ADVANCE_BATCH();
 118    }
 119
 120    if (hiz_mt == NULL) {
 121       BEGIN_BATCH(3);
 122       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 123       OUT_BATCH(0);
 124       OUT_BATCH(0);
 125       ADVANCE_BATCH();
 126    } else {
 127       BEGIN_BATCH(3);
 128       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 129       OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
 130       OUT_RELOC(hiz_mt->region->bo,
 131                 I915_GEM_DOMAIN_RENDER,
 132                 I915_GEM_DOMAIN_RENDER,
 133                 0);
 134       ADVANCE_BATCH();
 135    }
 136
 137    if (stencil_mt == NULL) {
 138       BEGIN_BATCH(3);
 139       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 140       OUT_BATCH(0);
 141       OUT_BATCH(0);
 142       ADVANCE_BATCH();
 143    } else {
 144       BEGIN_BATCH(3);
 145       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 146       OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
 147       OUT_RELOC(stencil_mt->region->bo,
 148                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 149                 0);
 150       ADVANCE_BATCH();
 151    }
 152
 153    BEGIN_BATCH(3);
 154    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 155    OUT_BATCH(0);
 156    OUT_BATCH(0);
 157    ADVANCE_BATCH();
 158 }
 159
 160 /**
 161  * \see brw_context.state.depth_region
 162  */
 163 const struct brw_tracked_state gen7_depthbuffer = {
 164    .dirty = {
 165       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 166       .brw = BRW_NEW_BATCH,
 167       .cache = 0,
 168    },
 169    .emit = emit_depthbuffer,
 170 };