src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_regions.h"
  26 #include "intel_fbo.h"
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30
  31 unsigned int
  32 gen7_depth_format(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct gl_framebuffer *fb = ctx->DrawBuffer;
  37    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  38    struct intel_region *region = NULL;
  39
  40    if (drb)
  41       region = drb->region;
  42    else
  43       return BRW_DEPTHFORMAT_D32_FLOAT;
  44
  45    switch (region->cpp) {
  46    case 2:
  47       return BRW_DEPTHFORMAT_D16_UNORM;
  48    case 4:
  49       if (intel->depth_buffer_is_float)
  50          return BRW_DEPTHFORMAT_D32_FLOAT;
  51       else
  52          return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
  53    default:
  54       assert(!"Should not get here.");
  55    }
  56    return 0;
  57 }
  58
  59 static void prepare_depthbuffer(struct brw_context *brw)
  60 {
  61    struct intel_context *intel = &brw->intel;
  62    struct gl_context *ctx = &intel->ctx;
  63    struct gl_framebuffer *fb = ctx->DrawBuffer;
  64    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  65    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  66
  67    if (drb)
  68       brw_add_validated_bo(brw, drb->region->bo);
  69    if (srb)
  70       brw_add_validated_bo(brw, srb->region->bo);
  71 }
  72
  73 static void emit_depthbuffer(struct brw_context *brw)
  74 {
  75    struct intel_context *intel = &brw->intel;
  76    struct gl_context *ctx = &intel->ctx;
  77    struct gl_framebuffer *fb = ctx->DrawBuffer;
  78
  79    /* _NEW_BUFFERS */
  80    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  81    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  82
  83    intel_emit_depth_stall_flushes(intel);
  84
  85    /* Gen7 doesn't support packed depth/stencil */
  86    assert(srb == NULL || srb != drb);
  87
  88    if (drb == NULL) {
  89       uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
  90       uint32_t dw3 = 0;
  91
  92       if (srb == NULL) {
  93          dw1 |= (BRW_SURFACE_NULL << 29);
  94       } else {
  95          struct intel_region *region = srb->region;
  96
  97          /* _NEW_STENCIL: enable stencil buffer writes */
  98          dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
  99
 100          /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
 101          dw1 |= (BRW_SURFACE_2D << 29);
 102          dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
 103       }
 104
 105       BEGIN_BATCH(7);
 106       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 107       OUT_BATCH(dw1);
 108       OUT_BATCH(0);
 109       OUT_BATCH(dw3);
 110       OUT_BATCH(0);
 111       OUT_BATCH(0);
 112       OUT_BATCH(0);
 113       ADVANCE_BATCH();
 114    } else {
 115       struct intel_region *region = drb->region;
 116       uint32_t tile_x, tile_y, offset;
 117
 118       offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
 119
 120       assert(region->tiling == I915_TILING_Y);
 121
 122       /* _NEW_DEPTH, _NEW_STENCIL */
 123       BEGIN_BATCH(7);
 124       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 125       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 126                 (gen7_depth_format(brw) << 18) |
 127                 (0 << 22) /* no HiZ buffer */ |
 128                 ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) |
 129                 ((ctx->Depth.Mask != 0) << 28) |
 130                 (BRW_SURFACE_2D << 29));
 131       OUT_RELOC(region->bo,
 132                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 133                 offset);
 134       OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
 135       OUT_BATCH(0);
 136       OUT_BATCH(tile_x | (tile_y << 16));
 137       OUT_BATCH(0);
 138       ADVANCE_BATCH();
 139    }
 140
 141    BEGIN_BATCH(4);
 142    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
 143    OUT_BATCH(0);
 144    OUT_BATCH(0);
 145    OUT_BATCH(0);
 146    ADVANCE_BATCH();
 147
 148    if (srb == NULL) {
 149       BEGIN_BATCH(3);
 150       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 151       OUT_BATCH(0);
 152       OUT_BATCH(0);
 153       ADVANCE_BATCH();
 154    } else {
 155       BEGIN_BATCH(3);
 156       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 157       OUT_BATCH(srb->region->pitch * srb->region->cpp - 1);
 158       OUT_RELOC(srb->region->bo,
 159                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 160                 0);
 161       ADVANCE_BATCH();
 162    }
 163
 164    BEGIN_BATCH(3);
 165    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 166    OUT_BATCH(0);
 167    OUT_BATCH(0);
 168    ADVANCE_BATCH();
 169 }
 170
 171 /**
 172  * \see brw_context.state.depth_region
 173  */
 174 const struct brw_tracked_state gen7_depthbuffer = {
 175    .dirty = {
 176       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 177       .brw = BRW_NEW_BATCH,
 178       .cache = 0,
 179    },
 180    .prepare = prepare_depthbuffer,
 181    .emit = emit_depthbuffer,
 182 };