src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31
  32 void
  33 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
  34                             struct intel_mipmap_tree *depth_mt,
  35                             uint32_t depth_offset, uint32_t depthbuffer_format,
  36                             uint32_t depth_surface_type,
  37                             struct intel_mipmap_tree *stencil_mt,
  38                             bool hiz, bool separate_stencil,
  39                             uint32_t width, uint32_t height,
  40                             uint32_t tile_x, uint32_t tile_y)
  41 {
  42    struct gl_context *ctx = &brw->ctx;
  43
  44    intel_emit_depth_stall_flushes(brw);
  45
  46    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
  47    BEGIN_BATCH(7);
  48    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  49    OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
  50              (depthbuffer_format << 18) |
  51              ((hiz ? 1 : 0) << 22) |
  52              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
  53              ((ctx->Depth.Mask != 0) << 28) |
  54              (depth_surface_type << 29));
  55
  56    if (depth_mt) {
  57       OUT_RELOC(depth_mt->region->bo,
  58                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  59                 depth_offset);
  60    } else {
  61       OUT_BATCH(0);
  62    }
  63
  64    OUT_BATCH(((width + tile_x - 1) << 4) |
  65              ((height + tile_y - 1) << 18));
  66    OUT_BATCH(0);
  67    OUT_BATCH(tile_x | (tile_y << 16));
  68    OUT_BATCH(0);
  69    ADVANCE_BATCH();
  70
  71    if (!hiz) {
  72       BEGIN_BATCH(3);
  73       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  74       OUT_BATCH(0);
  75       OUT_BATCH(0);
  76       ADVANCE_BATCH();
  77    } else {
  78       struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
  79       BEGIN_BATCH(3);
  80       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  81       OUT_BATCH(hiz_mt->region->pitch - 1);
  82       OUT_RELOC(hiz_mt->region->bo,
  83                 I915_GEM_DOMAIN_RENDER,
  84                 I915_GEM_DOMAIN_RENDER,
  85                 brw->depthstencil.hiz_offset);
  86       ADVANCE_BATCH();
  87    }
  88
  89    if (stencil_mt == NULL) {
  90       BEGIN_BATCH(3);
  91       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
  92       OUT_BATCH(0);
  93       OUT_BATCH(0);
  94       ADVANCE_BATCH();
  95    } else {
  96       const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
  97
  98       BEGIN_BATCH(3);
  99       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 100       /* The stencil buffer has quirky pitch requirements.  From the Graphics
 101        * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
 102        * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
 103        * field "Surface Pitch":
 104        *
 105        *    The pitch must be set to 2x the value computed based on width, as
 106        *    the stencil buffer is stored with two rows interleaved.
 107        *
 108        * (Note that it is not 100% clear whether this intended to apply to
 109        * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
 110        * imply that it doesn't), however the comment appears on a "DevIVB+"
 111        * page (which would imply that it does).  Experiments with the hardware
 112        * indicate that it does.
 113        */
 114       OUT_BATCH(enabled |
 115                 (2 * stencil_mt->region->pitch - 1));
 116       OUT_RELOC(stencil_mt->region->bo,
 117                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 118                 brw->depthstencil.stencil_offset);
 119       ADVANCE_BATCH();
 120    }
 121
 122    BEGIN_BATCH(3);
 123    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 124    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 125    OUT_BATCH(1);
 126    ADVANCE_BATCH();
 127 }
 128
 129 /**
 130  * \see brw_context.state.depth_region
 131  */
 132 const struct brw_tracked_state gen7_depthbuffer = {
 133    .dirty = {
 134       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 135       .brw = BRW_NEW_BATCH,
 136       .cache = 0,
 137    },
 138    .emit = brw_emit_depthbuffer,
 139 };