2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_regions.h"
27 #include "intel_fbo.h"
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 static void emit_depthbuffer(struct brw_context
*brw
)
34 struct intel_context
*intel
= &brw
->intel
;
35 struct gl_context
*ctx
= &intel
->ctx
;
36 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
39 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
40 struct intel_renderbuffer
*srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
41 struct intel_mipmap_tree
*depth_mt
= NULL
,
49 hiz_mt
= depth_mt
->hiz_mt
;
53 if (stencil_mt
->stencil_mt
)
54 stencil_mt
= stencil_mt
->stencil_mt
;
56 assert(stencil_mt
->format
== MESA_FORMAT_S8
);
59 /* Gen7 doesn't support packed depth/stencil */
60 assert(stencil_mt
== NULL
|| depth_mt
!= stencil_mt
);
61 assert(!depth_mt
|| !_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
63 intel_emit_depth_stall_flushes(intel
);
65 if (depth_mt
== NULL
) {
66 uint32_t dw1
= BRW_DEPTHFORMAT_D32_FLOAT
<< 18;
69 if (stencil_mt
== NULL
) {
70 dw1
|= (BRW_SURFACE_NULL
<< 29);
72 /* _NEW_STENCIL: enable stencil buffer writes */
73 dw1
|= ((ctx
->Stencil
.WriteMask
!= 0) << 27);
75 /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
76 dw1
|= (BRW_SURFACE_2D
<< 29);
77 dw3
= ((srb
->Base
.Width
- 1) << 4) |
78 ((srb
->Base
.Height
- 1) << 18);
82 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
91 struct intel_region
*region
= depth_mt
->region
;
92 uint32_t tile_x
, tile_y
, offset
;
94 offset
= intel_renderbuffer_tile_offsets(drb
, &tile_x
, &tile_y
);
96 assert(region
->tiling
== I915_TILING_Y
);
98 /* _NEW_DEPTH, _NEW_STENCIL */
100 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (7 - 2));
101 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
102 (brw_depthbuffer_format(brw
) << 18) |
103 ((hiz_mt
? 1 : 0) << 22) | /* hiz enable */
104 ((stencil_mt
!= NULL
&& ctx
->Stencil
.WriteMask
!= 0) << 27) |
105 ((ctx
->Depth
.Mask
!= 0) << 28) |
106 (BRW_SURFACE_2D
<< 29));
107 OUT_RELOC(region
->bo
,
108 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
110 OUT_BATCH(((drb
->Base
.Width
- 1) << 4) |
111 ((drb
->Base
.Height
- 1) << 18));
113 OUT_BATCH(tile_x
| (tile_y
<< 16));
118 if (hiz_mt
== NULL
) {
120 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
126 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (3 - 2));
127 OUT_BATCH(hiz_mt
->region
->pitch
* hiz_mt
->region
->cpp
- 1);
128 OUT_RELOC(hiz_mt
->region
->bo
,
129 I915_GEM_DOMAIN_RENDER
,
130 I915_GEM_DOMAIN_RENDER
,
135 if (stencil_mt
== NULL
) {
137 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
143 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (3 - 2));
144 OUT_BATCH(stencil_mt
->region
->pitch
* stencil_mt
->region
->cpp
- 1);
145 OUT_RELOC(stencil_mt
->region
->bo
,
146 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
152 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
159 * \see brw_context.state.depth_region
161 const struct brw_tracked_state gen7_depthbuffer
= {
163 .mesa
= (_NEW_BUFFERS
| _NEW_DEPTH
| _NEW_STENCIL
),
164 .brw
= BRW_NEW_BATCH
,
167 .emit
= emit_depthbuffer
,