src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31
  32 static void emit_depthbuffer(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct gl_framebuffer *fb = ctx->DrawBuffer;
  37
  38    /* _NEW_BUFFERS */
  39    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  40    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  41    struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
  42
  43    if (drb)
  44       depth_mt = drb->mt;
  45
  46    if (srb) {
  47       stencil_mt = srb->mt;
  48       if (stencil_mt->stencil_mt)
  49          stencil_mt = stencil_mt->stencil_mt;
  50
  51       assert(stencil_mt->format == MESA_FORMAT_S8);
  52    }
  53
  54    /* Gen7 doesn't support packed depth/stencil */
  55    assert(stencil_mt == NULL || depth_mt != stencil_mt);
  56    assert(!depth_mt || !_mesa_is_format_packed_depth_stencil(depth_mt->format));
  57
  58    intel_emit_depth_stall_flushes(intel);
  59
  60    if (depth_mt == NULL) {
  61       uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
  62       uint32_t dw3 = 0;
  63
  64       if (stencil_mt == NULL) {
  65          dw1 |= (BRW_SURFACE_NULL << 29);
  66       } else {
  67          struct intel_region *region = stencil_mt->region;
  68
  69          /* _NEW_STENCIL: enable stencil buffer writes */
  70          dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
  71
  72          /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
  73          dw1 |= (BRW_SURFACE_2D << 29);
  74          dw3 = ((srb->Base.Width - 1) << 4) |
  75                ((srb->Base.Height - 1) << 18);
  76       }
  77
  78       BEGIN_BATCH(7);
  79       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  80       OUT_BATCH(dw1);
  81       OUT_BATCH(0);
  82       OUT_BATCH(dw3);
  83       OUT_BATCH(0);
  84       OUT_BATCH(0);
  85       OUT_BATCH(0);
  86       ADVANCE_BATCH();
  87    } else {
  88       struct intel_region *region = depth_mt->region;
  89       uint32_t tile_x, tile_y, offset;
  90
  91       offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
  92
  93       assert(region->tiling == I915_TILING_Y);
  94
  95       /* _NEW_DEPTH, _NEW_STENCIL */
  96       BEGIN_BATCH(7);
  97       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  98       OUT_BATCH(((region->pitch * region->cpp) - 1) |
  99                 (brw_depthbuffer_format(brw) << 18) |
 100                 (0 << 22) /* no HiZ buffer */ |
 101                 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
 102                 ((ctx->Depth.Mask != 0) << 28) |
 103                 (BRW_SURFACE_2D << 29));
 104       OUT_RELOC(region->bo,
 105                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 106                 offset);
 107       OUT_BATCH(((drb->Base.Width - 1) << 4) |
 108                 ((drb->Base.Height - 1) << 18));
 109       OUT_BATCH(0);
 110       OUT_BATCH(tile_x | (tile_y << 16));
 111       OUT_BATCH(0);
 112       ADVANCE_BATCH();
 113    }
 114
 115    BEGIN_BATCH(4);
 116    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
 117    OUT_BATCH(0);
 118    OUT_BATCH(0);
 119    OUT_BATCH(0);
 120    ADVANCE_BATCH();
 121
 122    if (stencil_mt == NULL) {
 123       BEGIN_BATCH(3);
 124       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 125       OUT_BATCH(0);
 126       OUT_BATCH(0);
 127       ADVANCE_BATCH();
 128    } else {
 129       BEGIN_BATCH(3);
 130       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 131       OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
 132       OUT_RELOC(stencil_mt->region->bo,
 133                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 134                 0);
 135       ADVANCE_BATCH();
 136    }
 137
 138    BEGIN_BATCH(3);
 139    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 140    OUT_BATCH(0);
 141    OUT_BATCH(0);
 142    ADVANCE_BATCH();
 143 }
 144
 145 /**
 146  * \see brw_context.state.depth_region
 147  */
 148 const struct brw_tracked_state gen7_depthbuffer = {
 149    .dirty = {
 150       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 151       .brw = BRW_NEW_BATCH,
 152       .cache = 0,
 153    },
 154    .emit = emit_depthbuffer,
 155 };